From: Michael S. Tsirkin Subject: virtio-pci: define layout for virtio vendor-specific capabilities. Signed-off-by: Michael S. Tsirkin Signed-off-by: Rusty Russell --- include/linux/virtio_pci.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/include/linux/virtio_pci.h b/include/linux/virtio_pci.h index ea66f3f..d6568e7 100644 --- a/include/linux/virtio_pci.h +++ b/include/linux/virtio_pci.h @@ -92,4 +92,45 @@ /* The alignment to use between consumer and producer parts of vring. * x86 pagesize again. */ #define VIRTIO_PCI_VRING_ALIGN 4096 + +/* + * Layout for Virtio PCI vendor specific capability (little-endian): + * 5 bit virtio capability id. + * 3 bit BAR index register, specifying which BAR to use. + * 4 byte cfg offset within the BAR. + * 4 byte cfg size. + */ + +/* A single virtio device has multiple vendor specific capabilities, we use the + * 5 bit ID field to distinguish between these. */ +#define VIRTIO_PCI_CAP_ID 3 +#define VIRTIO_PCI_CAP_ID_MASK 0xff +#define VIRTIO_PCI_CAP_ID_SHIFT 0 + +/* IDs for different capabilities. If a specific configuration + * is missing, legacy PIO path is used. */ +/* Common configuration */ +#define VIRTIO_PCI_CAP_COMMON_CFG 1 +/* Notifications */ +#define VIRTIO_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define VIRTIO_PCI_CAP_ISR_CFG 3 +/* Device specific confiuration */ +#define VIRTIO_PCI_CAP_DEVICE_CFG 4 + +/* Index of the BAR including this configuration */ +#define VIRTIO_PCI_CAP_CFG_BIR 4 +#define VIRTIO_PCI_CAP_CFG_BIR_MASK (0x7) +#define VIRTIO_PCI_CAP_CFG_BIR_SHIFT 0 + +/* Size of the configuration space */ +#define VIRTIO_PCI_CAP_CFG_SIZE 4 +#define VIRTIO_PCI_CAP_CFG_SIZE_MASK 0xffffff +#define VIRTIO_PCI_CAP_CFG_SIZE_SHIFT 8 + +/* Offset within the BAR */ +#define VIRTIO_PCI_CAP_CFG_OFF 8 +#define VIRTIO_PCI_CAP_CFG_OFF_MASK 0xffffffff +#define VIRTIO_PCI_CAP_CFG_OFF_SHIFT 0 + #endif