/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */

module icache_64_8_4_2_8_12_56_16_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst, i_in, m_in, stall_in, flush_in, inval_in, wishbone_in, i_out, stall_out, wishbone_out, log_out);
  wire _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire [2:0] _012_;
  wire _013_;
  wire [2:0] _014_;
  wire _015_;
  wire _016_;
  wire _017_;
  wire [2:0] _018_;
  wire [2:0] _019_;
  wire _020_;
  wire _021_;
  wire [2:0] _022_;
  wire [2:0] _023_;
  wire [7:0] _024_;
  wire [7:0] _025_;
  wire [7:0] _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire _033_;
  wire _034_;
  wire _035_;
  wire _036_;
  wire [1:0] _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  wire _041_;
  wire _042_;
  wire [2:0] _043_;
  wire _044_;
  wire _045_;
  wire _046_;
  wire [1:0] _047_;
  wire _048_;
  wire _049_;
  wire _050_;
  wire [1:0] _051_;
  wire _052_;
  wire _053_;
  wire _054_;
  wire _055_;
  wire _056_;
  wire [2:0] _057_;
  wire _058_;
  wire _059_;
  wire _060_;
  wire [1:0] _061_;
  wire _062_;
  wire _063_;
  wire _064_;
  wire _065_;
  wire _066_;
  wire _067_;
  wire _068_;
  wire _069_;
  wire _070_;
  wire _071_;
  wire _072_;
  wire [1:0] _073_;
  wire _074_;
  wire _075_;
  wire _076_;
  wire _077_;
  wire _078_;
  wire _079_;
  wire _080_;
  wire _081_;
  wire _082_;
  wire _083_;
  wire [64:0] _084_;
  reg [66:0] _085_;
  wire [7:0] _086_;
  wire _087_;
  wire [2:0] _088_;
  wire [33:0] _089_;
  wire [1:0] _090_;
  wire [59:0] _091_;
  wire _092_;
  wire _093_;
  wire [1:0] _094_;
  wire _095_;
  wire [1:0] _096_;
  wire [1:0] _097_;
  wire [391:0] _098_;
  wire _099_;
  wire [1:0] _100_;
  wire [1:0] _101_;
  wire [391:0] _102_;
  wire [391:0] _103_;
  wire [7:0] _104_;
  wire [1:0] _105_;
  wire _106_;
  wire _107_;
  wire _108_;
  wire _109_;
  wire _110_;
  wire _111_;
  wire _112_;
  wire _113_;
  wire [2:0] _114_;
  wire [31:0] _115_;
  wire _116_;
  wire _117_;
  wire [2:0] _118_;
  wire _119_;
  wire _120_;
  wire [1:0] _121_;
  wire _122_;
  wire _123_;
  wire [7:0] _124_;
  wire [1:0] _125_;
  wire _126_;
  wire [2:0] _127_;
  wire _128_;
  wire _129_;
  wire _130_;
  wire [4:0] _131_;
  wire [7:0] _132_;
  wire _133_;
  wire _134_;
  wire _135_;
  wire [391:0] _136_;
  wire [7:0] _137_;
  wire [1:0] _138_;
  wire [31:0] _139_;
  wire _140_;
  wire _141_;
  wire _142_;
  wire [1:0] _143_;
  wire [4:0] _144_;
  wire [52:0] _145_;
  wire _146_;
  wire _147_;
  wire _148_;
  wire _149_;
  wire _150_;
  wire _151_;
  wire _152_;
  wire _153_;
  wire [391:0] _154_;
  wire [7:0] _155_;
  wire [33:0] _156_;
  wire [63:0] _157_;
  wire [1:0] _158_;
  wire [8:0] _159_;
  wire [68:0] _160_;
  wire _161_;
  wire _162_;
  wire _163_;
  wire _164_;
  wire _165_;
  wire _166_;
  wire _167_;
  wire _168_;
  reg [178:0] _169_;
  wire _170_;
  wire _171_;
  wire [511:0] _172_;
  wire [63:0] _173_;
  wire [391:0] _174_;
  wire [48:0] _175_;
  wire _176_;
  wire _177_;
  wire _178_;
  wire _179_;
  wire _180_;
  wire _181_;
  wire _182_;
  wire _183_;
  wire _184_;
  wire _185_;
  wire _186_;
  wire _187_;
  wire _188_;
  wire _189_;
  wire _190_;
  wire _191_;
  wire _192_;
  wire _193_;
  wire _194_;
  wire _195_;
  wire _196_;
  wire _197_;
  wire _198_;
  wire _199_;
  wire _200_;
  wire _201_;
  wire _202_;
  wire _203_;
  wire _204_;
  wire _205_;
  wire _206_;
  wire _207_;
  wire _208_;
  wire _209_;
  wire _210_;
  wire _211_;
  wire _212_;
  wire _213_;
  wire _214_;
  wire _215_;
  wire _216_;
  wire _217_;
  wire _218_;
  wire _219_;
  wire _220_;
  wire _221_;
  wire _222_;
  wire _223_;
  wire _224_;
  wire _225_;
  wire _226_;
  wire _227_;
  wire _228_;
  wire [97:0] _229_;
  wire _230_;
  wire _231_;
  wire _232_;
  wire _233_;
  wire [97:0] _234_;
  wire _235_;
  wire [63:0] _236_;
  wire [31:0] _237_;
  wire _238_;
  wire _239_;
  wire _240_;
  wire _241_;
  wire _242_;
  wire _243_;
  wire _244_;
  wire _245_;
  wire _246_;
  wire _247_;
  wire _248_;
  wire _249_;
  wire _250_;
  wire _251_;
  wire _252_;
  wire _253_;
  wire _254_;
  wire _255_;
  wire _256_;
  wire _257_;
  wire _258_;
  wire _259_;
  wire _260_;
  wire [97:0] _261_;
  wire _262_;
  wire _263_;
  wire _264_;
  wire _265_;
  wire _266_;
  wire _267_;
  wire [97:0] _268_;
  wire [97:0] _269_;
  wire [97:0] _270_;
  wire [97:0] _271_;
  wire [97:0] _272_;
  wire _273_;
  wire _274_;
  wire _275_;
  wire _276_;
  wire _277_;
  wire _278_;
  wire [97:0] _279_;
  wire [97:0] _280_;
  wire [97:0] _281_;
  wire [97:0] _282_;
  wire _283_;
  wire _284_;
  wire _285_;
  wire _286_;
  wire _287_;
  wire _288_;
  wire _289_;
  wire _290_;
  wire _291_;
  wire _292_;
  wire _293_;
  wire _294_;
  wire _295_;
  wire _296_;
  wire _297_;
  wire _298_;
  wire _299_;
  wire _300_;
  wire _301_;
  wire _302_;
  wire _303_;
  wire _304_;
  wire _305_;
  wire _306_;
  wire _307_;
  wire _308_;
  wire _309_;
  wire _310_;
  wire _311_;
  wire _312_;
  wire _313_;
  wire _314_;
  wire _315_;
  wire _316_;
  wire _317_;
  wire _318_;
  wire _319_;
  wire _320_;
  wire _321_;
  wire _322_;
  wire _323_;
  wire _324_;
  wire _325_;
  wire _326_;
  wire _327_;
  wire _328_;
  wire _329_;
  wire _330_;
  wire _331_;
  wire _332_;
  wire _333_;
  wire [97:0] _334_;
  wire _335_;
  wire _336_;
  wire _337_;
  wire [97:0] _338_;
  wire _339_;
  wire [97:0] _340_;
  wire [97:0] _341_;
  wire _342_;
  wire _343_;
  wire _344_;
  wire _345_;
  wire _346_;
  wire [97:0] _347_;
  wire _348_;
  wire _349_;
  wire _350_;
  wire [97:0] _351_;
  wire _352_;
  wire [97:0] _353_;
  wire [97:0] _354_;
  wire access_ok;
  reg [391:0] cache_tags;
  reg [7:0] cache_valids;
  input clk;
  wire eaa_priv;
  input flush_in;
  input [69:0] i_in;
  output [98:0] i_out;
  reg [53:0] \icache_log.log_data ;
  input inval_in;
  reg [7:0] itlb_valids;
  output [53:0] log_out;
  input [130:0] m_in;
  wire \maybe_plrus.plrus:0.plru_acc_en ;
  wire \maybe_plrus.plrus:0.plru_out ;
  wire \maybe_plrus.plrus:1.plru_acc_en ;
  wire \maybe_plrus.plrus:1.plru_out ;
  wire \maybe_plrus.plrus:2.plru_acc_en ;
  wire \maybe_plrus.plrus:2.plru_out ;
  wire \maybe_plrus.plrus:3.plru_acc_en ;
  wire \maybe_plrus.plrus:3.plru_out ;
  wire priv_fault;
  wire ra_valid;
  wire \rams:0.do_read ;
  wire \rams:0.do_write ;
  wire [63:0] \rams:0.dout ;
  wire [63:0] \rams:0.wr_dat ;
  wire \rams:1.do_read ;
  wire \rams:1.do_write ;
  wire [63:0] \rams:1.dout ;
  wire [63:0] \rams:1.wr_dat ;
  wire [55:0] real_addr;
  wire replace_way;
  wire req_hit_way;
  wire req_is_hit;
  wire req_is_miss;
  input rst;
  input stall_in;
  output stall_out;
  wire [2:0] tlb_req_index;
  wire use_previous;
  input [65:0] wishbone_in;
  output [106:0] wishbone_out;
  reg [63:0] \$mem$\4543  [7:0];
  reg [48:0] \$mem$\4546  [7:0];
  (* ram_style = "distributed" *)
  reg [63:0] \4543  [7:0];
  always @(posedge clk) begin
    if (_034_) \4543 [_019_] <= m_in[130:67];
  end
  assign _173_ = \4543 [tlb_req_index];
  (* ram_style = "distributed" *)
  reg [48:0] \4546  [7:0];
  always @(posedge clk) begin
    if (_030_) \4546 [_019_] <= m_in[66:18];
  end
  assign _175_ = \4546 [tlb_req_index];
  assign _329_ = _014_[0] ? itlb_valids[1] : itlb_valids[0];
  assign _330_ = _014_[0] ? itlb_valids[5] : itlb_valids[4];
  assign _331_ = _037_[0] ? cache_valids[2] : cache_valids[0];
  assign _332_ = _043_[0] ? _169_[171] : _169_[170];
  assign _333_ = _043_[0] ? _169_[175] : _169_[174];
  assign _334_ = _047_[0] ? cache_tags[195:98] : cache_tags[97:0];
  assign _335_ = _051_[0] ? cache_valids[3] : cache_valids[1];
  assign _336_ = _057_[0] ? _169_[171] : _169_[170];
  assign _337_ = _057_[0] ? _169_[175] : _169_[174];
  assign _338_ = _061_[0] ? cache_tags[195:98] : cache_tags[97:0];
  assign _339_ = _073_[0] ? \maybe_plrus.plrus:2.plru_out  : \maybe_plrus.plrus:3.plru_out ;
  assign _340_ = _096_[0] ? cache_tags[195:98] : cache_tags[97:0];
  assign _341_ = _100_[0] ? cache_tags[195:98] : cache_tags[97:0];
  assign _342_ = _014_[0] ? itlb_valids[3] : itlb_valids[2];
  assign _343_ = _014_[0] ? itlb_valids[7] : itlb_valids[6];
  assign _344_ = _037_[0] ? cache_valids[6] : cache_valids[4];
  assign _345_ = _043_[0] ? _169_[173] : _169_[172];
  assign _346_ = _043_[0] ? _169_[177] : _169_[176];
  assign _347_ = _047_[0] ? cache_tags[391:294] : cache_tags[293:196];
  assign _348_ = _051_[0] ? cache_valids[7] : cache_valids[5];
  assign _349_ = _057_[0] ? _169_[173] : _169_[172];
  assign _350_ = _057_[0] ? _169_[177] : _169_[176];
  assign _351_ = _061_[0] ? cache_tags[391:294] : cache_tags[293:196];
  assign _352_ = _073_[0] ? \maybe_plrus.plrus:0.plru_out  : \maybe_plrus.plrus:1.plru_out ;
  assign _353_ = _096_[0] ? cache_tags[391:294] : cache_tags[293:196];
  assign _354_ = _100_[0] ? cache_tags[391:294] : cache_tags[293:196];
  assign _176_ = _014_[1] ? _342_ : _329_;
  assign _177_ = _014_[1] ? _343_ : _330_;
  assign _225_ = _037_[1] ? _344_ : _331_;
  assign _226_ = _043_[1] ? _345_ : _332_;
  assign _227_ = _043_[1] ? _346_ : _333_;
  assign _229_ = _047_[1] ? _347_ : _334_;
  assign _230_ = _051_[1] ? _348_ : _335_;
  assign _231_ = _057_[1] ? _349_ : _336_;
  assign _232_ = _057_[1] ? _350_ : _337_;
  assign _234_ = _061_[1] ? _351_ : _338_;
  assign _235_ = _073_[1] ? _352_ : _339_;
  assign _261_ = _096_[1] ? _353_ : _340_;
  assign _272_ = _100_[1] ? _354_ : _341_;
  assign _000_ = ~ _169_[165];
  assign \rams:0.wr_dat  = _000_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
  assign _001_ = stall_in | use_previous;
  assign \rams:0.do_read  = ~ _001_;
  assign _002_ = { 31'h00000000, replace_way } == 32'd0;
  assign _003_ = wishbone_in[64] & _002_;
  assign \rams:0.do_write  = _003_ ? 1'h1 : 1'h0;
  assign _004_ = ~ _169_[165];
  assign \rams:1.wr_dat  = _004_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
  assign _005_ = stall_in | use_previous;
  assign \rams:1.do_read  = ~ _005_;
  assign _006_ = { 31'h00000000, replace_way } == 32'd1;
  assign _007_ = wishbone_in[64] & _006_;
  assign \rams:1.do_write  = _007_ ? 1'h1 : 1'h0;
  assign _008_ = { 30'h00000000, _085_[8:7] } == 32'd0;
  assign \maybe_plrus.plrus:0.plru_acc_en  = _008_ ? _085_[66] : 1'h0;
  assign _009_ = { 30'h00000000, _085_[8:7] } == 32'd1;
  assign \maybe_plrus.plrus:1.plru_acc_en  = _009_ ? _085_[66] : 1'h0;
  assign _010_ = { 30'h00000000, _085_[8:7] } == 32'd2;
  assign \maybe_plrus.plrus:2.plru_acc_en  = _010_ ? _085_[66] : 1'h0;
  assign _011_ = { 30'h00000000, _085_[8:7] } == 32'd3;
  assign \maybe_plrus.plrus:3.plru_acc_en  = _011_ ? _085_[66] : 1'h0;
  assign _012_ = i_in[20:18] ^ i_in[23:21];
  assign tlb_req_index = _012_ ^ i_in[26:24];
  assign _013_ = _175_ == i_in[69:21];
  assign _014_ = 3'h7 - tlb_req_index;
  assign _015_ = _013_ ? _178_ : 1'h0;
  assign eaa_priv = i_in[1] ? _173_[3] : 1'h1;
  assign real_addr = i_in[1] ? { _173_[55:12], i_in[17:6] } : i_in[61:6];
  assign ra_valid = i_in[1] ? _015_ : 1'h1;
  assign _016_ = ~ i_in[2];
  assign priv_fault = eaa_priv & _016_;
  assign _017_ = ~ priv_fault;
  assign access_ok = ra_valid & _017_;
  assign _018_ = m_in[17:15] ^ m_in[20:18];
  assign _019_ = _018_ ^ m_in[23:21];
  assign _020_ = m_in[1] & m_in[2];
  assign _021_ = rst | _020_;
  assign _022_ = 3'h7 - _019_;
  assign _023_ = 3'h7 - _019_;
  assign _024_ = m_in[0] ? { _224_, _223_, _222_, _221_, _220_, _219_, _218_, _217_ } : itlb_valids;
  assign _025_ = m_in[1] ? { _201_, _200_, _199_, _198_, _197_, _196_, _195_, _194_ } : _024_;
  assign _026_ = _021_ ? 8'h00 : _025_;
  always @(posedge clk)
    itlb_valids <= _026_;
  assign _027_ = ~ _021_;
  assign _028_ = ~ m_in[1];
  assign _029_ = _027_ & _028_;
  assign _030_ = _029_ & m_in[0];
  assign _031_ = ~ _021_;
  assign _032_ = ~ m_in[1];
  assign _033_ = _031_ & _032_;
  assign _034_ = _033_ & m_in[0];
  assign _035_ = i_in[8] != 1'h0;
  assign _036_ = i_in[5] & _085_[66];
  assign use_previous = _035_ ? _036_ : 1'h0;
  assign _037_ = 2'h3 - i_in[13:12];
  assign _038_ = _169_[1:0] == 2'h2;
  assign _039_ = { 30'h00000000, i_in[13:12] } == { 30'h00000000, _169_[111:110] };
  assign _040_ = _038_ & _039_;
  assign _041_ = 32'd0 == { 31'h00000000, _169_[109] };
  assign _042_ = _040_ & _041_;
  assign _043_ = 3'h7 - i_in[11:9];
  assign _044_ = _042_ & _228_;
  assign _045_ = _225_ | _044_;
  assign _046_ = i_in[0] & _045_;
  assign _047_ = 2'h3 - i_in[13:12];
  assign _048_ = _229_[48:0] == { i_in[3], real_addr[55:8] };
  assign _049_ = _048_ ? 1'h1 : 1'h0;
  assign _050_ = _046_ ? _049_ : 1'h0;
  assign _051_ = 2'h3 - i_in[13:12];
  assign _052_ = _169_[1:0] == 2'h2;
  assign _053_ = { 30'h00000000, i_in[13:12] } == { 30'h00000000, _169_[111:110] };
  assign _054_ = _052_ & _053_;
  assign _055_ = 32'd1 == { 31'h00000000, _169_[109] };
  assign _056_ = _054_ & _055_;
  assign _057_ = 3'h7 - i_in[11:9];
  assign _058_ = _056_ & _233_;
  assign _059_ = _230_ | _058_;
  assign _060_ = i_in[0] & _059_;
  assign _061_ = 2'h3 - i_in[13:12];
  assign _062_ = _234_[97:49] == { i_in[3], real_addr[55:8] };
  assign _063_ = _065_ ? 1'h1 : _050_;
  assign _064_ = _062_ ? 1'h1 : 1'h0;
  assign _065_ = _060_ & _062_;
  assign req_hit_way = _060_ ? _064_ : 1'h0;
  assign _066_ = i_in[0] & access_ok;
  assign _067_ = ~ flush_in;
  assign _068_ = _066_ & _067_;
  assign _069_ = ~ rst;
  assign _070_ = _068_ & _069_;
  assign _071_ = ~ _063_;
  assign req_is_hit = _070_ ? _063_ : 1'h0;
  assign req_is_miss = _070_ ? _071_ : 1'h0;
  assign _072_ = _169_[1:0] == 2'h1;
  assign _073_ = 2'h3 - _169_[111:110];
  assign replace_way = _072_ ? _235_ : _169_[109];
  assign _074_ = 1'h1 - _085_[0];
  assign _075_ = _063_ & access_ok;
  assign _076_ = ~ _075_;
  assign _077_ = stall_in | use_previous;
  assign _078_ = rst | flush_in;
  assign _079_ = _078_ ? 1'h0 : _085_[66];
  assign _080_ = req_is_hit ? req_hit_way : _085_[0];
  assign _081_ = _077_ ? _085_[0] : _080_;
  assign _082_ = _077_ ? _079_ : req_is_hit;
  assign _083_ = ~ stall_in;
  assign _084_ = _083_ ? { i_in[4], i_in[69:6] } : _085_[65:1];
  always @(posedge clk)
    _085_ <= { _082_, _084_, _081_ };
  assign _086_ = inval_in ? 8'h00 : cache_valids;
  assign _087_ = inval_in ? 1'h0 : _169_[166];
  assign _088_ = real_addr[5:3] - 3'h1;
  assign _089_ = req_is_miss ? { real_addr[31:3], 5'h01 } : _169_[33:0];
  assign _090_ = req_is_miss ? 2'h3 : _169_[99:98];
  assign _091_ = req_is_miss ? { _088_, 1'h1, i_in[3], real_addr[55:3], i_in[13:12] } : { _169_[169:167], _087_, _169_[165:110] };
  assign _092_ = _169_[1:0] == 2'h0;
  assign _093_ = _169_[1:0] == 2'h1;
  assign _094_ = 2'h3 - i_in[13:12];
  assign _095_ = 32'd0 == { 31'h00000000, replace_way };
  assign _096_ = 2'h3 - _169_[111:110];
  assign _097_ = 2'h3 - _169_[111:110];
  assign _098_ = _095_ ? { _271_, _270_, _269_, _268_ } : cache_tags;
  assign _099_ = 32'd1 == { 31'h00000000, replace_way };
  assign _100_ = 2'h3 - _169_[111:110];
  assign _101_ = 2'h3 - _169_[111:110];
  assign _102_ = _099_ ? { _282_, _281_, _280_, _279_ } : _098_;
  assign _103_ = _093_ ? _102_ : cache_tags;
  assign _104_ = _093_ ? { _260_, _259_, _258_, _257_, _256_, _255_, _254_, _253_ } : _086_;
  assign _105_ = _093_ ? 2'h2 : _169_[1:0];
  assign _106_ = _093_ ? replace_way : _169_[109];
  assign _107_ = ~ _169_[99];
  assign _108_ = ~ wishbone_in[65];
  assign _109_ = ~ _107_;
  assign _110_ = _108_ & _109_;
  assign _111_ = _169_[7:5] == _169_[169:167];
  assign _112_ = _116_ ? 1'h0 : _169_[99];
  assign _113_ = _117_ ? 1'h1 : _107_;
  assign _114_ = _169_[7:5] + 3'h1;
  assign _115_ = _110_ ? { _169_[33:8], _114_, _169_[4:2] } : _169_[33:2];
  assign _116_ = _110_ & _111_;
  assign _117_ = _110_ & _111_;
  assign _118_ = 3'h7 - _169_[114:112];
  assign _119_ = _169_[114:112] == _169_[169:167];
  assign _120_ = _113_ & _119_;
  assign _121_ = 2'h3 - _169_[111:110];
  assign _122_ = ~ inval_in;
  assign _123_ = _169_[166] & _122_;
  assign _124_ = _128_ ? { _328_, _327_, _326_, _325_, _324_, _323_, _322_, _321_ } : _104_;
  assign _125_ = _129_ ? 2'h0 : _105_;
  assign _126_ = _130_ ? 1'h0 : _169_[98];
  assign _127_ = _169_[114:112] + 3'h1;
  assign _128_ = wishbone_in[64] & _120_;
  assign _129_ = wishbone_in[64] & _120_;
  assign _130_ = wishbone_in[64] & _120_;
  assign _131_ = wishbone_in[64] ? { _169_[116:115], _127_ } : _169_[116:112];
  assign _132_ = wishbone_in[64] ? { _305_, _304_, _303_, _302_, _301_, _300_, _299_, _298_ } : _169_[177:170];
  assign _133_ = _169_[1:0] == 2'h1;
  assign _134_ = _169_[1:0] == 2'h2;
  assign _135_ = _133_ | _134_;
  function [391:0] \4387 ;
    input [391:0] a;
    input [783:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4387  = b[391:0];
      2'b1?:
        \4387  = b[783:392];
      default:
        \4387  = a;
    endcase
  endfunction
  assign _136_ = \4387 (392'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _103_, cache_tags }, { _135_, _092_ });
  function [7:0] \4389 ;
    input [7:0] a;
    input [15:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4389  = b[7:0];
      2'b1?:
        \4389  = b[15:8];
      default:
        \4389  = a;
    endcase
  endfunction
  assign _137_ = \4389 (8'hxx, { _124_, _086_ }, { _135_, _092_ });
  function [1:0] \4392 ;
    input [1:0] a;
    input [3:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4392  = b[1:0];
      2'b1?:
        \4392  = b[3:2];
      default:
        \4392  = a;
    endcase
  endfunction
  assign _138_ = \4392 (2'hx, { _125_, _089_[1:0] }, { _135_, _092_ });
  function [31:0] \4395 ;
    input [31:0] a;
    input [63:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4395  = b[31:0];
      2'b1?:
        \4395  = b[63:32];
      default:
        \4395  = a;
    endcase
  endfunction
  assign _139_ = \4395 (32'hxxxxxxxx, { _115_, _089_[33:2] }, { _135_, _092_ });
  function [0:0] \4398 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4398  = b[0:0];
      2'b1?:
        \4398  = b[1:1];
      default:
        \4398  = a;
    endcase
  endfunction
  assign _140_ = \4398 (1'hx, { _126_, _090_[0] }, { _135_, _092_ });
  function [0:0] \4401 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4401  = b[0:0];
      2'b1?:
        \4401  = b[1:1];
      default:
        \4401  = a;
    endcase
  endfunction
  assign _141_ = \4401 (1'hx, { _112_, _090_[1] }, { _135_, _092_ });
  function [0:0] \4404 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4404  = b[0:0];
      2'b1?:
        \4404  = b[1:1];
      default:
        \4404  = a;
    endcase
  endfunction
  assign _142_ = \4404 (1'hx, { _106_, _169_[109] }, { _135_, _092_ });
  function [1:0] \4408 ;
    input [1:0] a;
    input [3:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4408  = b[1:0];
      2'b1?:
        \4408  = b[3:2];
      default:
        \4408  = a;
    endcase
  endfunction
  assign _143_ = \4408 (2'hx, { _169_[111:110], _091_[1:0] }, { _135_, _092_ });
  function [4:0] \4411 ;
    input [4:0] a;
    input [9:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4411  = b[4:0];
      2'b1?:
        \4411  = b[9:5];
      default:
        \4411  = a;
    endcase
  endfunction
  assign _144_ = \4411 (5'hxx, { _131_, _091_[6:2] }, { _135_, _092_ });
  function [52:0] \4417 ;
    input [52:0] a;
    input [105:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4417  = b[52:0];
      2'b1?:
        \4417  = b[105:53];
      default:
        \4417  = a;
    endcase
  endfunction
  assign _145_ = \4417 (53'hxxxxxxxxxxxxxx, { _169_[169:167], _087_, _169_[165:117], _091_[59:7] }, { _135_, _092_ });
  function [0:0] \4420 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4420  = b[0:0];
      2'b1?:
        \4420  = b[1:1];
      default:
        \4420  = a;
    endcase
  endfunction
  assign _146_ = \4420 (1'hx, { _132_[0], 1'h0 }, { _135_, _092_ });
  function [0:0] \4423 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4423  = b[0:0];
      2'b1?:
        \4423  = b[1:1];
      default:
        \4423  = a;
    endcase
  endfunction
  assign _147_ = \4423 (1'hx, { _132_[1], 1'h0 }, { _135_, _092_ });
  function [0:0] \4426 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4426  = b[0:0];
      2'b1?:
        \4426  = b[1:1];
      default:
        \4426  = a;
    endcase
  endfunction
  assign _148_ = \4426 (1'hx, { _132_[2], 1'h0 }, { _135_, _092_ });
  function [0:0] \4429 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4429  = b[0:0];
      2'b1?:
        \4429  = b[1:1];
      default:
        \4429  = a;
    endcase
  endfunction
  assign _149_ = \4429 (1'hx, { _132_[3], 1'h0 }, { _135_, _092_ });
  function [0:0] \4432 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4432  = b[0:0];
      2'b1?:
        \4432  = b[1:1];
      default:
        \4432  = a;
    endcase
  endfunction
  assign _150_ = \4432 (1'hx, { _132_[4], 1'h0 }, { _135_, _092_ });
  function [0:0] \4435 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4435  = b[0:0];
      2'b1?:
        \4435  = b[1:1];
      default:
        \4435  = a;
    endcase
  endfunction
  assign _151_ = \4435 (1'hx, { _132_[5], 1'h0 }, { _135_, _092_ });
  function [0:0] \4438 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4438  = b[0:0];
      2'b1?:
        \4438  = b[1:1];
      default:
        \4438  = a;
    endcase
  endfunction
  assign _152_ = \4438 (1'hx, { _132_[6], 1'h0 }, { _135_, _092_ });
  function [0:0] \4441 ;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* parallel_case *)
    casez (s)
      2'b?1:
        \4441  = b[0:0];
      2'b1?:
        \4441  = b[1:1];
      default:
        \4441  = a;
    endcase
  endfunction
  assign _153_ = \4441 (1'hx, { _132_[7], 1'h0 }, { _135_, _092_ });
  assign _154_ = rst ? cache_tags : _136_;
  assign _155_ = rst ? 8'h00 : _137_;
  assign _156_ = rst ? 34'h000000000 : { _139_, _138_ };
  assign _157_ = rst ? 64'h0000000000000000 : _169_[97:34];
  assign _158_ = rst ? 2'h0 : { _141_, _140_ };
  assign _159_ = rst ? 9'h0ff : _169_[108:100];
  assign _160_ = rst ? _169_[177:109] : { _153_, _152_, _151_, _150_, _149_, _148_, _147_, _146_, _145_, _144_, _143_, _142_ };
  assign _161_ = rst | flush_in;
  assign _162_ = _161_ | m_in[0];
  assign _163_ = ~ access_ok;
  assign _164_ = i_in[0] & _163_;
  assign _165_ = ~ stall_in;
  assign _166_ = _164_ & _165_;
  assign _167_ = _166_ ? 1'h1 : _169_[178];
  assign _168_ = _162_ ? 1'h0 : _167_;
  always @(posedge clk)
    cache_tags <= _154_;
  always @(posedge clk)
    cache_valids <= _155_;
  always @(posedge clk)
    _169_ <= { _168_, _160_, _159_, _158_, _157_, _156_ };
  assign _170_ = _169_[1:0] != 2'h0;
  assign _171_ = _170_ ? 1'h1 : 1'h0;
  always @(posedge clk)
    \icache_log.log_data  <= { _085_[66], _237_, wishbone_in[64], _169_[7:5], _169_[99:98], wishbone_in[65], _076_, _169_[178], _085_[6:3], _171_, 2'h0, req_hit_way, req_is_hit, req_is_miss, access_ok, ra_valid };
  assign _178_ = _014_[2] ? _177_ : _176_;
  assign _179_ = ~ _022_[2];
  assign _180_ = ~ _022_[1];
  assign _181_ = _179_ & _180_;
  assign _182_ = _179_ & _022_[1];
  assign _183_ = _022_[2] & _180_;
  assign _184_ = _022_[2] & _022_[1];
  assign _185_ = ~ _022_[0];
  assign _186_ = _181_ & _185_;
  assign _187_ = _181_ & _022_[0];
  assign _188_ = _182_ & _185_;
  assign _189_ = _182_ & _022_[0];
  assign _190_ = _183_ & _185_;
  assign _191_ = _183_ & _022_[0];
  assign _192_ = _184_ & _185_;
  assign _193_ = _184_ & _022_[0];
  assign _194_ = _186_ ? 1'h0 : itlb_valids[0];
  assign _195_ = _187_ ? 1'h0 : itlb_valids[1];
  assign _196_ = _188_ ? 1'h0 : itlb_valids[2];
  assign _197_ = _189_ ? 1'h0 : itlb_valids[3];
  assign _198_ = _190_ ? 1'h0 : itlb_valids[4];
  assign _199_ = _191_ ? 1'h0 : itlb_valids[5];
  assign _200_ = _192_ ? 1'h0 : itlb_valids[6];
  assign _201_ = _193_ ? 1'h0 : itlb_valids[7];
  assign _202_ = ~ _023_[2];
  assign _203_ = ~ _023_[1];
  assign _204_ = _202_ & _203_;
  assign _205_ = _202_ & _023_[1];
  assign _206_ = _023_[2] & _203_;
  assign _207_ = _023_[2] & _023_[1];
  assign _208_ = ~ _023_[0];
  assign _209_ = _204_ & _208_;
  assign _210_ = _204_ & _023_[0];
  assign _211_ = _205_ & _208_;
  assign _212_ = _205_ & _023_[0];
  assign _213_ = _206_ & _208_;
  assign _214_ = _206_ & _023_[0];
  assign _215_ = _207_ & _208_;
  assign _216_ = _207_ & _023_[0];
  assign _217_ = _209_ ? 1'h1 : itlb_valids[0];
  assign _218_ = _210_ ? 1'h1 : itlb_valids[1];
  assign _219_ = _211_ ? 1'h1 : itlb_valids[2];
  assign _220_ = _212_ ? 1'h1 : itlb_valids[3];
  assign _221_ = _213_ ? 1'h1 : itlb_valids[4];
  assign _222_ = _214_ ? 1'h1 : itlb_valids[5];
  assign _223_ = _215_ ? 1'h1 : itlb_valids[6];
  assign _224_ = _216_ ? 1'h1 : itlb_valids[7];
  assign _228_ = _043_[2] ? _227_ : _226_;
  assign _233_ = _057_[2] ? _232_ : _231_;
  assign _236_ = _074_ ? \rams:0.dout  : \rams:1.dout ;
  assign _237_ = _085_[3] ? _236_[63:32] : _236_[31:0];
  assign _238_ = ~ _094_[1];
  assign _239_ = ~ _094_[0];
  assign _240_ = _238_ & _239_;
  assign _241_ = _238_ & _094_[0];
  assign _242_ = _094_[1] & _239_;
  assign _243_ = _094_[1] & _094_[0];
  assign _244_ = ~ replace_way;
  assign _245_ = _240_ & _244_;
  assign _246_ = _240_ & replace_way;
  assign _247_ = _241_ & _244_;
  assign _248_ = _241_ & replace_way;
  assign _249_ = _242_ & _244_;
  assign _250_ = _242_ & replace_way;
  assign _251_ = _243_ & _244_;
  assign _252_ = _243_ & replace_way;
  assign _253_ = _245_ ? 1'h0 : _086_[0];
  assign _254_ = _246_ ? 1'h0 : _086_[1];
  assign _255_ = _247_ ? 1'h0 : _086_[2];
  assign _256_ = _248_ ? 1'h0 : _086_[3];
  assign _257_ = _249_ ? 1'h0 : _086_[4];
  assign _258_ = _250_ ? 1'h0 : _086_[5];
  assign _259_ = _251_ ? 1'h0 : _086_[6];
  assign _260_ = _252_ ? 1'h0 : _086_[7];
  assign _262_ = ~ _097_[1];
  assign _263_ = ~ _097_[0];
  assign _264_ = _262_ & _263_;
  assign _265_ = _262_ & _097_[0];
  assign _266_ = _097_[1] & _263_;
  assign _267_ = _097_[1] & _097_[0];
  assign _268_ = _264_ ? { _261_[97:49], _169_[165:117] } : cache_tags[97:0];
  assign _269_ = _265_ ? { _261_[97:49], _169_[165:117] } : cache_tags[195:98];
  assign _270_ = _266_ ? { _261_[97:49], _169_[165:117] } : cache_tags[293:196];
  assign _271_ = _267_ ? { _261_[97:49], _169_[165:117] } : cache_tags[391:294];
  assign _273_ = ~ _101_[1];
  assign _274_ = ~ _101_[0];
  assign _275_ = _273_ & _274_;
  assign _276_ = _273_ & _101_[0];
  assign _277_ = _101_[1] & _274_;
  assign _278_ = _101_[1] & _101_[0];
  assign _279_ = _275_ ? { _169_[165:117], _272_[48:0] } : _098_[97:0];
  assign _280_ = _276_ ? { _169_[165:117], _272_[48:0] } : _098_[195:98];
  assign _281_ = _277_ ? { _169_[165:117], _272_[48:0] } : _098_[293:196];
  assign _282_ = _278_ ? { _169_[165:117], _272_[48:0] } : _098_[391:294];
  assign _283_ = ~ _118_[2];
  assign _284_ = ~ _118_[1];
  assign _285_ = _283_ & _284_;
  assign _286_ = _283_ & _118_[1];
  assign _287_ = _118_[2] & _284_;
  assign _288_ = _118_[2] & _118_[1];
  assign _289_ = ~ _118_[0];
  assign _290_ = _285_ & _289_;
  assign _291_ = _285_ & _118_[0];
  assign _292_ = _286_ & _289_;
  assign _293_ = _286_ & _118_[0];
  assign _294_ = _287_ & _289_;
  assign _295_ = _287_ & _118_[0];
  assign _296_ = _288_ & _289_;
  assign _297_ = _288_ & _118_[0];
  assign _298_ = _290_ ? 1'h1 : _169_[170];
  assign _299_ = _291_ ? 1'h1 : _169_[171];
  assign _300_ = _292_ ? 1'h1 : _169_[172];
  assign _301_ = _293_ ? 1'h1 : _169_[173];
  assign _302_ = _294_ ? 1'h1 : _169_[174];
  assign _303_ = _295_ ? 1'h1 : _169_[175];
  assign _304_ = _296_ ? 1'h1 : _169_[176];
  assign _305_ = _297_ ? 1'h1 : _169_[177];
  assign _306_ = ~ _121_[1];
  assign _307_ = ~ _121_[0];
  assign _308_ = _306_ & _307_;
  assign _309_ = _306_ & _121_[0];
  assign _310_ = _121_[1] & _307_;
  assign _311_ = _121_[1] & _121_[0];
  assign _312_ = ~ replace_way;
  assign _313_ = _308_ & _312_;
  assign _314_ = _308_ & replace_way;
  assign _315_ = _309_ & _312_;
  assign _316_ = _309_ & replace_way;
  assign _317_ = _310_ & _312_;
  assign _318_ = _310_ & replace_way;
  assign _319_ = _311_ & _312_;
  assign _320_ = _311_ & replace_way;
  assign _321_ = _313_ ? _123_ : _104_[0];
  assign _322_ = _314_ ? _123_ : _104_[1];
  assign _323_ = _315_ ? _123_ : _104_[2];
  assign _324_ = _316_ ? _123_ : _104_[3];
  assign _325_ = _317_ ? _123_ : _104_[4];
  assign _326_ = _318_ ? _123_ : _104_[5];
  assign _327_ = _319_ ? _123_ : _104_[6];
  assign _328_ = _320_ ? _123_ : _104_[7];
  plru_1 \maybe_plrus.plrus:0.plru  (
    .acc(_085_[0]),
    .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:0.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:1.plru  (
    .acc(_085_[0]),
    .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:1.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:2.plru  (
    .acc(_085_[0]),
    .acc_en(\maybe_plrus.plrus:2.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:2.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:3.plru  (
    .acc(_085_[0]),
    .acc_en(\maybe_plrus.plrus:3.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:3.plru_out ),
    .rst(rst)
  );
  cache_ram_5_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:0.way  (
    .clk(clk),
    .rd_addr(i_in[13:9]),
    .rd_data(\rams:0.dout ),
    .rd_en(\rams:0.do_read ),
    .wr_addr(_169_[116:112]),
    .wr_data(\rams:0.wr_dat ),
    .wr_sel({ \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write  })
  );
  cache_ram_5_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:1.way  (
    .clk(clk),
    .rd_addr(i_in[13:9]),
    .rd_data(\rams:1.dout ),
    .rd_en(\rams:1.do_read ),
    .wr_addr(_169_[116:112]),
    .wr_data(\rams:1.wr_dat ),
    .wr_sel({ \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write  })
  );
  assign i_out = { _237_, _085_[64:1], _169_[178], _085_[65], _085_[66] };
  assign stall_out = _076_;
  assign wishbone_out = _169_[108:2];
  assign log_out = \icache_log.log_data ;
endmodule

module cache_ram_5_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
  wire [255:0] _00_;
  wire [7:0] _01_;
  wire [255:0] _02_;
  wire [7:0] _03_;
  wire [255:0] _04_;
  wire [7:0] _05_;
  wire [255:0] _06_;
  wire [7:0] _07_;
  wire [255:0] _08_;
  wire [7:0] _09_;
  wire [255:0] _10_;
  wire [7:0] _11_;
  wire [255:0] _12_;
  wire [7:0] _13_;
  wire [255:0] _14_;
  wire [7:0] _15_;
  input clk;
  input [4:0] rd_addr;
  output [63:0] rd_data;
  input rd_en;
  input [4:0] wr_addr;
  input [63:0] wr_data;
  input [7:0] wr_sel;
  reg [7:0] \$mem$\17257  [31:0];
  reg [7:0] \$mem$\17258  [31:0];
  reg [7:0] \$mem$\17259  [31:0];
  reg [7:0] \$mem$\17260  [31:0];
  reg [7:0] \$mem$\17261  [31:0];
  reg [7:0] \$mem$\17262  [31:0];
  reg [7:0] \$mem$\17263  [31:0];
  reg [7:0] \$mem$\17264  [31:0];
  (* ram_style = "block" *)
  reg [7:0] \17257  [31:0];
  reg [7:0] _16_;
  always @(posedge clk) begin
    if (rd_en) _16_ <= \17257 [rd_addr];
    if (wr_sel[0]) \17257 [wr_addr] <= wr_data[7:0];
  end
  assign _01_ = _16_;
  (* ram_style = "block" *)
  reg [7:0] \17258  [31:0];
  reg [7:0] _17_;
  always @(posedge clk) begin
    if (rd_en) _17_ <= \17258 [rd_addr];
    if (wr_sel[1]) \17258 [wr_addr] <= wr_data[15:8];
  end
  assign _03_ = _17_;
  (* ram_style = "block" *)
  reg [7:0] \17259  [31:0];
  reg [7:0] _18_;
  always @(posedge clk) begin
    if (rd_en) _18_ <= \17259 [rd_addr];
    if (wr_sel[2]) \17259 [wr_addr] <= wr_data[23:16];
  end
  assign _05_ = _18_;
  (* ram_style = "block" *)
  reg [7:0] \17260  [31:0];
  reg [7:0] _19_;
  always @(posedge clk) begin
    if (rd_en) _19_ <= \17260 [rd_addr];
    if (wr_sel[3]) \17260 [wr_addr] <= wr_data[31:24];
  end
  assign _07_ = _19_;
  (* ram_style = "block" *)
  reg [7:0] \17261  [31:0];
  reg [7:0] _20_;
  always @(posedge clk) begin
    if (rd_en) _20_ <= \17261 [rd_addr];
    if (wr_sel[4]) \17261 [wr_addr] <= wr_data[39:32];
  end
  assign _09_ = _20_;
  (* ram_style = "block" *)
  reg [7:0] \17262  [31:0];
  reg [7:0] _21_;
  always @(posedge clk) begin
    if (rd_en) _21_ <= \17262 [rd_addr];
    if (wr_sel[5]) \17262 [wr_addr] <= wr_data[47:40];
  end
  assign _11_ = _21_;
  (* ram_style = "block" *)
  reg [7:0] \17263  [31:0];
  reg [7:0] _22_;
  always @(posedge clk) begin
    if (rd_en) _22_ <= \17263 [rd_addr];
    if (wr_sel[6]) \17263 [wr_addr] <= wr_data[55:48];
  end
  assign _13_ = _22_;
  (* ram_style = "block" *)
  reg [7:0] \17264  [31:0];
  reg [7:0] _23_;
  always @(posedge clk) begin
    if (rd_en) _23_ <= \17264 [rd_addr];
    if (wr_sel[7]) \17264 [wr_addr] <= wr_data[63:56];
  end
  assign _15_ = _23_;
  assign rd_data = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
endmodule

module plru_1(clk, rst, acc, acc_en, lru);
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  input acc;
  input acc_en;
  input clk;
  output lru;
  input rst;
  reg [1:0] tree;
  assign _0_ = ~ acc;
  assign _1_ = acc_en ? _0_ : tree[1];
  assign _2_ = rst ? 1'h0 : tree[0];
  assign _3_ = rst ? 1'h0 : _1_;
  always @(posedge clk)
    tree <= { _3_, _2_ };
  assign lru = tree[1];
endmodule