/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */

module dcache_64_4_2_4_2_12_16(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out, log_out);
  wire _000_;
  wire _001_;
  wire [146:0] _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire [146:0] _006_;
  wire _007_;
  wire [146:0] _008_;
  wire _009_;
  wire _010_;
  wire [1:0] _011_;
  wire _012_;
  wire [1:0] _013_;
  wire [1:0] _014_;
  wire _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire [1:0] _030_;
  wire [7:0] _031_;
  wire [1:0] _032_;
  wire _033_;
  wire [1:0] _034_;
  wire [7:0] _035_;
  wire [7:0] _036_;
  wire [7:0] _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  wire _041_;
  wire _042_;
  wire _043_;
  wire _044_;
  wire _045_;
  wire _046_;
  wire _047_;
  wire _048_;
  wire _049_;
  wire [1:0] _050_;
  wire [1:0] _051_;
  wire _052_;
  wire _053_;
  wire _054_;
  wire _055_;
  wire [1:0] _056_;
  wire _057_;
  wire _058_;
  wire _059_;
  wire _060_;
  wire _061_;
  wire _062_;
  wire [1:0] _063_;
  wire _064_;
  wire _065_;
  wire _066_;
  wire _067_;
  wire _068_;
  wire _069_;
  wire _070_;
  wire _071_;
  wire [1:0] _072_;
  wire _073_;
  wire _074_;
  wire _075_;
  wire _076_;
  wire _077_;
  wire _078_;
  wire [1:0] _079_;
  wire _080_;
  wire _081_;
  wire _082_;
  wire _083_;
  wire _084_;
  wire _085_;
  wire _086_;
  wire _087_;
  wire _088_;
  wire _089_;
  wire _090_;
  wire _091_;
  wire [1:0] _092_;
  wire _093_;
  wire _094_;
  wire _095_;
  wire _096_;
  wire [1:0] _097_;
  wire _098_;
  wire _099_;
  wire _100_;
  wire _101_;
  wire _102_;
  wire _103_;
  wire _104_;
  wire _105_;
  wire _106_;
  wire _107_;
  wire _108_;
  wire _109_;
  wire _110_;
  wire _111_;
  wire [2:0] _112_;
  wire _113_;
  wire _114_;
  wire _115_;
  wire _116_;
  wire _117_;
  wire _118_;
  wire _119_;
  wire _120_;
  wire [1:0] _121_;
  wire _122_;
  wire _123_;
  wire _124_;
  wire _125_;
  wire _126_;
  wire _127_;
  wire _128_;
  wire _129_;
  wire _130_;
  wire _131_;
  wire _132_;
  wire _133_;
  wire _134_;
  wire _135_;
  wire _136_;
  wire _137_;
  wire [2:0] _138_;
  wire [2:0] _139_;
  wire [2:0] _140_;
  wire _141_;
  wire [4:0] _142_;
  wire _143_;
  wire _144_;
  wire _145_;
  wire _146_;
  wire _147_;
  wire _148_;
  wire _149_;
  wire _150_;
  wire _151_;
  wire [58:0] _152_;
  wire _153_;
  wire [57:0] _154_;
  wire [58:0] _155_;
  wire _156_;
  wire [57:0] _157_;
  wire [63:0] _158_;
  wire _159_;
  wire [7:0] _160_;
  wire [7:0] _161_;
  wire [7:0] _162_;
  wire [7:0] _163_;
  wire [7:0] _164_;
  wire [7:0] _165_;
  wire [7:0] _166_;
  wire [7:0] _167_;
  wire _168_;
  wire _169_;
  wire _170_;
  wire [63:0] _171_;
  wire _172_;
  wire _173_;
  wire _174_;
  wire _175_;
  wire _176_;
  wire _177_;
  wire _178_;
  wire [63:0] _179_;
  wire _180_;
  wire _181_;
  wire _182_;
  wire _183_;
  wire _184_;
  wire _185_;
  wire _186_;
  wire _187_;
  wire _188_;
  wire _189_;
  wire _190_;
  wire _191_;
  wire _192_;
  wire _193_;
  wire [1:0] _194_;
  wire _195_;
  wire _196_;
  wire _197_;
  reg _198_;
  reg [8:0] _199_;
  reg _200_;
  reg [2:0] _201_;
  wire [7:0] _202_;
  wire [7:0] _203_;
  wire [63:0] _204_;
  wire [63:0] _205_;
  wire _206_;
  wire _207_;
  wire _208_;
  wire _209_;
  wire _210_;
  wire _211_;
  wire _212_;
  wire _213_;
  wire _214_;
  wire _215_;
  wire _216_;
  wire _217_;
  wire _218_;
  wire _219_;
  wire _220_;
  wire [63:0] _221_;
  wire _222_;
  wire _223_;
  wire _224_;
  wire [7:0] _225_;
  wire _226_;
  wire _227_;
  wire _228_;
  wire _229_;
  wire _230_;
  wire _231_;
  wire _232_;
  wire _233_;
  wire _234_;
  wire [135:0] _235_;
  wire [2:0] _236_;
  wire _237_;
  wire _238_;
  wire _239_;
  wire _240_;
  wire _241_;
  wire _242_;
  wire _243_;
  wire _244_;
  wire _245_;
  wire _246_;
  wire _247_;
  wire _248_;
  wire _249_;
  wire _250_;
  wire [1:0] _251_;
  wire _252_;
  wire _253_;
  wire _254_;
  wire [2:0] _255_;
  wire _256_;
  wire _257_;
  wire _258_;
  wire _259_;
  wire _260_;
  wire _261_;
  wire _262_;
  wire _263_;
  wire _264_;
  wire [1:0] _265_;
  wire _266_;
  wire _267_;
  wire _268_;
  wire _269_;
  wire _270_;
  wire _271_;
  wire [2:0] _272_;
  wire _273_;
  wire _274_;
  wire _275_;
  wire _276_;
  wire _277_;
  wire _278_;
  wire _279_;
  wire _280_;
  wire _281_;
  wire _282_;
  wire [2:0] _283_;
  wire [31:0] _284_;
  wire _285_;
  wire _286_;
  wire [2:0] _287_;
  wire _288_;
  wire _289_;
  wire _290_;
  wire _291_;
  wire _292_;
  wire _293_;
  wire _294_;
  wire _295_;
  wire _296_;
  wire _297_;
  wire _298_;
  wire _299_;
  wire _300_;
  wire [8:0] _301_;
  wire _302_;
  wire _303_;
  wire _304_;
  wire _305_;
  wire _306_;
  wire [1:0] _307_;
  wire [7:0] _308_;
  wire [1:0] _309_;
  wire _310_;
  wire [2:0] _311_;
  wire _312_;
  wire _313_;
  wire [10:0] _314_;
  wire _315_;
  wire _316_;
  wire [4:0] _317_;
  wire [7:0] _318_;
  wire _319_;
  wire _320_;
  wire _321_;
  wire _322_;
  wire _323_;
  wire [2:0] _324_;
  wire [2:0] _325_;
  wire [2:0] _326_;
  wire [2:0] _327_;
  wire _328_;
  wire [7:0] _329_;
  wire [63:0] _330_;
  wire [7:0] _331_;
  wire _332_;
  wire _333_;
  wire _334_;
  wire _335_;
  wire _336_;
  wire _337_;
  wire _338_;
  wire _339_;
  wire _340_;
  wire _341_;
  wire _342_;
  wire _343_;
  wire _344_;
  wire _345_;
  wire _346_;
  wire _347_;
  wire _348_;
  wire [8:0] _349_;
  wire _350_;
  wire _351_;
  wire _352_;
  wire _353_;
  wire _354_;
  wire _355_;
  wire [1:0] _356_;
  wire _357_;
  wire [1:0] _358_;
  wire _359_;
  wire _360_;
  wire [1:0] _361_;
  wire _362_;
  wire [7:0] _363_;
  wire _364_;
  wire _365_;
  wire _366_;
  wire _367_;
  wire _368_;
  wire _369_;
  wire _370_;
  wire [10:0] _371_;
  wire _372_;
  wire [1:0] _373_;
  wire _374_;
  wire _375_;
  wire _376_;
  wire [7:0] _377_;
  wire _378_;
  wire _379_;
  wire _380_;
  wire _381_;
  wire _382_;
  wire _383_;
  wire [8:0] _384_;
  wire [1:0] _385_;
  wire _386_;
  wire _387_;
  wire _388_;
  wire _389_;
  wire [7:0] _390_;
  wire [23:0] _391_;
  wire [63:0] _392_;
  wire _393_;
  wire _394_;
  wire [7:0] _395_;
  wire _396_;
  wire [47:0] _397_;
  wire _398_;
  wire [4:0] _399_;
  wire [1:0] _400_;
  wire [2:0] _401_;
  wire _402_;
  wire _403_;
  wire _404_;
  wire _405_;
  wire _406_;
  wire _407_;
  wire _408_;
  wire _409_;
  wire [2:0] _410_;
  wire _411_;
  wire _412_;
  wire _413_;
  wire _414_;
  wire _415_;
  wire _416_;
  wire [133:0] _417_;
  wire [133:0] _418_;
  wire [7:0] _419_;
  wire _420_;
  wire [135:0] _421_;
  wire _422_;
  wire _423_;
  wire [8:0] _424_;
  wire [1:0] _425_;
  wire [2:0] _426_;
  wire [32:0] _427_;
  wire [63:0] _428_;
  wire [1:0] _429_;
  wire [80:0] _430_;
  wire _431_;
  wire _432_;
  wire [5:0] _433_;
  wire [7:0] _434_;
  wire _435_;
  wire _436_;
  wire _437_;
  wire _438_;
  reg _439_;
  reg [135:0] _440_;
  reg [337:0] _441_;
  reg _442_;
  wire [399:0] _443_;
  wire [511:0] _444_;
  wire [191:0] _445_;
  wire [47:0] _446_;
  wire [191:0] _447_;
  wire [47:0] _448_;
  wire [1:0] _449_;
  wire [63:0] _450_;
  wire _451_;
  wire _452_;
  wire _453_;
  wire _454_;
  wire _455_;
  wire _456_;
  wire _457_;
  wire _458_;
  wire _459_;
  wire _460_;
  wire _461_;
  wire _462_;
  wire _463_;
  wire _464_;
  wire _465_;
  wire _466_;
  wire _467_;
  wire _468_;
  wire _469_;
  wire _470_;
  wire _471_;
  wire _472_;
  wire _473_;
  wire _474_;
  wire _475_;
  wire [49:0] _476_;
  wire [49:0] _477_;
  wire _478_;
  wire [63:0] _479_;
  wire [63:0] _480_;
  wire _481_;
  wire _482_;
  wire _483_;
  wire _484_;
  wire _485_;
  wire _486_;
  wire _487_;
  wire _488_;
  wire _489_;
  wire _490_;
  wire _491_;
  wire _492_;
  wire _493_;
  wire _494_;
  wire _495_;
  wire _496_;
  wire _497_;
  wire _498_;
  wire _499_;
  wire _500_;
  wire _501_;
  wire _502_;
  wire _503_;
  wire _504_;
  wire _505_;
  wire _506_;
  wire _507_;
  wire _508_;
  wire _509_;
  wire _510_;
  wire _511_;
  wire _512_;
  wire _513_;
  wire _514_;
  wire _515_;
  wire _516_;
  wire [63:0] _517_;
  wire _518_;
  wire _519_;
  wire _520_;
  wire _521_;
  wire _522_;
  wire _523_;
  wire _524_;
  wire _525_;
  wire _526_;
  wire _527_;
  wire _528_;
  wire _529_;
  wire _530_;
  wire _531_;
  wire _532_;
  wire _533_;
  wire _534_;
  wire _535_;
  wire _536_;
  wire _537_;
  wire _538_;
  wire _539_;
  wire _540_;
  wire _541_;
  wire _542_;
  wire _543_;
  wire _544_;
  wire _545_;
  wire _546_;
  wire _547_;
  wire _548_;
  wire _549_;
  wire _550_;
  wire _551_;
  wire _552_;
  wire _553_;
  wire _554_;
  wire _555_;
  wire _556_;
  wire _557_;
  wire _558_;
  wire _559_;
  wire _560_;
  wire _561_;
  wire _562_;
  wire _563_;
  wire [1:0] _564_;
  wire _565_;
  wire _566_;
  wire _567_;
  wire _568_;
  wire _569_;
  wire _570_;
  wire _571_;
  wire _572_;
  wire _573_;
  wire _574_;
  wire [1:0] _575_;
  wire _576_;
  wire _577_;
  wire _578_;
  wire _579_;
  wire _580_;
  wire _581_;
  wire _582_;
  wire _583_;
  wire _584_;
  wire _585_;
  wire access_ok;
  reg [7:0] cache_valids;
  wire cancel_store;
  wire clear_rsrv;
  input clk;
  input [142:0] d_in;
  output [67:0] d_out;
  reg [19:0] \dc_log.log_data ;
  reg [7:0] dtlb_valids;
  wire [4:0] early_req_row;
  output [19:0] log_out;
  input [131:0] m_in;
  output [66:0] m_out;
  wire \maybe_plrus.plrus:0.plru_acc_en ;
  wire \maybe_plrus.plrus:0.plru_out ;
  wire \maybe_plrus.plrus:1.plru_acc_en ;
  wire \maybe_plrus.plrus:1.plru_out ;
  wire \maybe_plrus.plrus:2.plru_acc_en ;
  wire \maybe_plrus.plrus:2.plru_out ;
  wire \maybe_plrus.plrus:3.plru_acc_en ;
  wire \maybe_plrus.plrus:3.plru_out ;
  wire \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en ;
  wire \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out ;
  wire \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en ;
  wire \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ;
  wire \maybe_tlb_plrus.tlb_plrus:2.tlb_plru_acc_en ;
  wire \maybe_tlb_plrus.tlb_plrus:2.tlb_plru_out ;
  wire \maybe_tlb_plrus.tlb_plrus:3.tlb_plru_acc_en ;
  wire \maybe_tlb_plrus.tlb_plrus:3.tlb_plru_out ;
  wire [5:0] perm_attr;
  wire perm_ok;
  wire [63:0] pte;
  reg [146:0] r0;
  reg r0_full;
  wire r0_stall;
  wire r0_valid;
  wire [55:0] ra;
  wire \rams:0.do_write ;
  wire [63:0] \rams:0.dout ;
  wire [4:0] \rams:0.wr_addr ;
  wire [63:0] \rams:0.wr_data ;
  wire [7:0] \rams:0.wr_sel ;
  wire [7:0] \rams:0.wr_sel_m ;
  wire \rams:1.do_write ;
  wire [63:0] \rams:1.dout ;
  wire [4:0] \rams:1.wr_addr ;
  wire [63:0] \rams:1.wr_data ;
  wire [7:0] \rams:1.wr_sel ;
  wire [7:0] \rams:1.wr_sel_m ;
  wire rc_ok;
  wire replace_way;
  wire req_go;
  wire req_hit_way;
  wire [2:0] req_op;
  wire req_same_tag;
  reg [58:0] reservation;
  input rst;
  wire set_rsrv;
  output stall_out;
  wire tlb_hit;
  wire tlb_hit_way;
  wire [127:0] tlb_pte_way;
  wire [99:0] tlb_tag_way;
  reg [1:0] tlb_valid_way;
  wire use_forward1_next;
  wire use_forward2_next;
  wire valid_ra;
  input [65:0] wishbone_in;
  output [106:0] wishbone_out;
  reg [99:0] \$mem$\16011  [3:0];
  reg [127:0] \$mem$\16014  [3:0];
  reg [47:0] \$mem$\16017  [3:0];
  reg [47:0] \$mem$\16018  [3:0];
  (* ram_style = "distributed" *)
  reg [99:0] \16011  [3:0];
  reg [99:0] _619_;
  always @(posedge clk) begin
    if (_012_) _619_ <= \16011 [_011_];
    if (_041_) \16011 [r0[20:19]] <= { _477_, _476_ };
  end
  assign tlb_tag_way = _619_;
  (* ram_style = "distributed" *)
  reg [127:0] \16014  [3:0];
  reg [127:0] _620_;
  always @(posedge clk) begin
    if (_012_) _620_ <= \16014 [_011_];
    if (_045_) \16014 [r0[20:19]] <= { _480_, _479_ };
  end
  assign tlb_pte_way = _620_;
  (* ram_style = "distributed" *)
  reg [47:0] \16017  [3:0];
  reg [47:0] _621_;
  always @(posedge clk) begin
    _621_ <= \16017 [_051_];
    if (_438_) \16017 [_441_[320:319]] <= _441_[312:265];
  end
  assign _446_ = _621_;
  (* ram_style = "distributed" *)
  reg [47:0] \16018  [3:0];
  reg [47:0] _622_;
  always @(posedge clk) begin
    _622_ <= \16018 [_051_];
    if (_437_) \16018 [_441_[320:319]] <= _441_[312:265];
  end
  assign _448_ = _622_;
  assign _564_ = _013_[0] ? dtlb_valids[3:2] : dtlb_valids[1:0];
  assign _565_ = _032_[0] ? \maybe_tlb_plrus.tlb_plrus:2.tlb_plru_out  : \maybe_tlb_plrus.tlb_plrus:3.tlb_plru_out ;
  assign _566_ = _056_[0] ? cache_valids[2] : cache_valids[0];
  assign _567_ = _063_[0] ? cache_valids[3] : cache_valids[1];
  assign _568_ = _072_[0] ? cache_valids[2] : cache_valids[0];
  assign _569_ = _079_[0] ? cache_valids[3] : cache_valids[1];
  assign _570_ = _092_[0] ? cache_valids[2] : cache_valids[0];
  assign _571_ = _097_[0] ? cache_valids[3] : cache_valids[1];
  assign _572_ = _112_[0] ? _441_[325] : _441_[324];
  assign _573_ = _112_[0] ? _441_[329] : _441_[328];
  assign _574_ = _121_[0] ? \maybe_plrus.plrus:2.plru_out  : \maybe_plrus.plrus:3.plru_out ;
  assign _575_ = _013_[0] ? dtlb_valids[7:6] : dtlb_valids[5:4];
  assign _576_ = _032_[0] ? \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out  : \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ;
  assign _577_ = _056_[0] ? cache_valids[6] : cache_valids[4];
  assign _578_ = _063_[0] ? cache_valids[7] : cache_valids[5];
  assign _579_ = _072_[0] ? cache_valids[6] : cache_valids[4];
  assign _580_ = _079_[0] ? cache_valids[7] : cache_valids[5];
  assign _581_ = _092_[0] ? cache_valids[6] : cache_valids[4];
  assign _582_ = _097_[0] ? cache_valids[7] : cache_valids[5];
  assign _583_ = _112_[0] ? _441_[327] : _441_[326];
  assign _584_ = _112_[0] ? _441_[331] : _441_[330];
  assign _585_ = _121_[0] ? \maybe_plrus.plrus:0.plru_out  : \maybe_plrus.plrus:1.plru_out ;
  assign _449_ = _013_[1] ? _575_ : _564_;
  assign _474_ = _032_[1] ? _576_ : _565_;
  assign _504_ = _056_[1] ? _577_ : _566_;
  assign _505_ = _063_[1] ? _578_ : _567_;
  assign _506_ = _072_[1] ? _579_ : _568_;
  assign _507_ = _079_[1] ? _580_ : _569_;
  assign _511_ = _092_[1] ? _581_ : _570_;
  assign _512_ = _097_[1] ? _582_ : _571_;
  assign _513_ = _112_[1] ? _583_ : _572_;
  assign _514_ = _112_[1] ? _584_ : _573_;
  assign _516_ = _121_[1] ? _585_ : _574_;
  assign _000_ = m_in[1] | m_in[3];
  assign _001_ = ~ _000_;
  assign _002_ = m_in[0] ? { 1'h1, m_in[3:1], 8'hff, m_in[131:4], 5'h10, _001_, 1'h1 } : { 4'h0, d_in };
  assign _003_ = ~ _439_;
  assign _004_ = ~ r0_full;
  assign _005_ = _003_ | _004_;
  assign _006_ = _005_ ? _002_ : r0;
  assign _007_ = _005_ ? _002_[0] : r0_full;
  assign _008_ = rst ? r0 : _006_;
  assign _009_ = rst ? 1'h0 : _007_;
  always @(posedge clk)
    r0 <= _008_;
  always @(posedge clk)
    r0_full <= _009_;
  assign r0_stall = r0_full & _439_;
  assign _010_ = ~ _439_;
  assign r0_valid = r0_full & _010_;
  assign _011_ = m_in[0] ? m_in[17:16] : d_in[20:19];
  assign _012_ = ~ r0_stall;
  assign _013_ = 2'h3 - _011_;
  assign _014_ = _012_ ? _449_ : tlb_valid_way;
  always @(posedge clk)
    tlb_valid_way <= _014_;
  assign _015_ = { 30'h00000000, _199_[8:7] } == 32'd0;
  assign \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en  = _015_ ? _199_[5] : 1'h0;
  assign _016_ = { 30'h00000000, _199_[8:7] } == 32'd1;
  assign \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en  = _016_ ? _199_[5] : 1'h0;
  assign _017_ = { 30'h00000000, _199_[8:7] } == 32'd2;
  assign \maybe_tlb_plrus.tlb_plrus:2.tlb_plru_acc_en  = _017_ ? _199_[5] : 1'h0;
  assign _018_ = { 30'h00000000, _199_[8:7] } == 32'd3;
  assign \maybe_tlb_plrus.tlb_plrus:3.tlb_plru_acc_en  = _018_ ? _199_[5] : 1'h0;
  assign _019_ = tlb_tag_way[49:0] == r0[70:21];
  assign _020_ = tlb_valid_way[0] & _019_;
  assign _021_ = _020_ ? 1'h1 : 1'h0;
  assign _022_ = tlb_tag_way[99:50] == r0[70:21];
  assign _023_ = tlb_valid_way[1] & _022_;
  assign tlb_hit_way = _023_ ? 1'h1 : 1'h0;
  assign _024_ = _023_ ? 1'h1 : _021_;
  assign tlb_hit = _024_ & r0_valid;
  assign pte = tlb_hit ? _450_ : 64'h0000000000000000;
  assign _025_ = ~ r0[5];
  assign valid_ra = tlb_hit | _025_;
  assign ra = r0[5] ? { pte[55:12], r0[18:10], 3'h0 } : { r0[62:10], 3'h0 };
  assign perm_attr = r0[5] ? { pte[1], pte[2], pte[3], pte[5], pte[7], pte[8] } : 6'h3b;
  assign _026_ = r0_valid & r0[143];
  assign _027_ = r0_valid & r0[145];
  assign _028_ = _026_ & r0[144];
  assign _029_ = rst | _028_;
  assign _030_ = 2'h3 - r0[20:19];
  assign _031_ = tlb_hit ? { _473_, _472_, _471_, _470_, _469_, _468_, _467_, _466_ } : dtlb_valids;
  assign _032_ = 2'h3 - r0[20:19];
  assign _033_ = tlb_hit ? tlb_hit_way : _474_;
  assign _034_ = 2'h3 - r0[20:19];
  assign _035_ = _027_ ? { _503_, _502_, _501_, _500_, _499_, _498_, _497_, _496_ } : dtlb_valids;
  assign _036_ = _026_ ? _031_ : _035_;
  assign _037_ = _029_ ? 8'h00 : _036_;
  always @(posedge clk)
    dtlb_valids <= _037_;
  assign _038_ = ~ _029_;
  assign _039_ = ~ _026_;
  assign _040_ = _038_ & _039_;
  assign _041_ = _040_ & _027_;
  assign _042_ = ~ _029_;
  assign _043_ = ~ _026_;
  assign _044_ = _042_ & _043_;
  assign _045_ = _044_ & _027_;
  assign _046_ = { 30'h00000000, _199_[3:2] } == 32'd0;
  assign \maybe_plrus.plrus:0.plru_acc_en  = _046_ ? _199_[4] : 1'h0;
  assign _047_ = { 30'h00000000, _199_[3:2] } == 32'd1;
  assign \maybe_plrus.plrus:1.plru_acc_en  = _047_ ? _199_[4] : 1'h0;
  assign _048_ = { 30'h00000000, _199_[3:2] } == 32'd2;
  assign \maybe_plrus.plrus:2.plru_acc_en  = _048_ ? _199_[4] : 1'h0;
  assign _049_ = { 30'h00000000, _199_[3:2] } == 32'd3;
  assign \maybe_plrus.plrus:3.plru_acc_en  = _049_ ? _199_[4] : 1'h0;
  assign _050_ = m_in[0] ? m_in[11:10] : d_in[14:13];
  assign _051_ = r0_stall ? r0[14:13] : _050_;
  assign _052_ = r0[143] | r0[145];
  assign _053_ = ~ _052_;
  assign _054_ = r0_valid & _053_;
  assign _055_ = ~ _200_;
  assign req_go = _054_ & _055_;
  assign _056_ = 2'h3 - r0[14:13];
  assign _057_ = req_go & _504_;
  assign _058_ = _446_ == { tlb_pte_way[55:12], r0[18:15] };
  assign _059_ = _057_ & _058_;
  assign _060_ = _059_ & tlb_valid_way[0];
  assign _061_ = _060_ ? 1'h1 : 1'h0;
  assign _062_ = _060_ ? 1'h0 : 1'h0;
  assign _063_ = 2'h3 - r0[14:13];
  assign _064_ = req_go & _505_;
  assign _065_ = _448_ == { tlb_pte_way[55:12], r0[18:15] };
  assign _066_ = _064_ & _065_;
  assign _067_ = _066_ & tlb_valid_way[0];
  assign _068_ = _067_ ? 1'h1 : _061_;
  assign _069_ = _067_ ? 1'h1 : _062_;
  assign _070_ = { tlb_pte_way[55:12], r0[18:15] } == _441_[312:265];
  assign _071_ = _070_ ? 1'h1 : 1'h0;
  assign _072_ = 2'h3 - r0[14:13];
  assign _073_ = req_go & _506_;
  assign _074_ = _446_ == { tlb_pte_way[119:76], r0[18:15] };
  assign _075_ = _073_ & _074_;
  assign _076_ = _075_ & tlb_valid_way[1];
  assign _077_ = _076_ ? 1'h1 : 1'h0;
  assign _078_ = _076_ ? 1'h0 : 1'h0;
  assign _079_ = 2'h3 - r0[14:13];
  assign _080_ = req_go & _507_;
  assign _081_ = _448_ == { tlb_pte_way[119:76], r0[18:15] };
  assign _082_ = _080_ & _081_;
  assign _083_ = _082_ & tlb_valid_way[1];
  assign _084_ = _083_ ? 1'h1 : _077_;
  assign _085_ = _083_ ? 1'h1 : _078_;
  assign _086_ = { tlb_pte_way[119:76], r0[18:15] } == _441_[312:265];
  assign _087_ = _086_ ? 1'h1 : 1'h0;
  assign _088_ = 1'h1 - tlb_hit_way;
  assign _089_ = tlb_hit ? _508_ : 1'h0;
  assign _090_ = tlb_hit ? _509_ : 1'h0;
  assign _091_ = tlb_hit ? _510_ : 1'h0;
  assign _092_ = 2'h3 - r0[14:13];
  assign _093_ = req_go & _511_;
  assign _094_ = _446_ == r0[62:15];
  assign _095_ = _093_ & _094_;
  assign _096_ = _095_ ? 1'h1 : 1'h0;
  assign _097_ = 2'h3 - r0[14:13];
  assign _098_ = req_go & _512_;
  assign _099_ = _448_ == r0[62:15];
  assign _100_ = _098_ & _099_;
  assign _101_ = _100_ ? 1'h1 : _096_;
  assign _102_ = _100_ ? 1'h1 : 1'h0;
  assign _103_ = r0[62:15] == _441_[312:265];
  assign _104_ = _103_ ? 1'h1 : 1'h0;
  assign _105_ = r0[5] ? _089_ : _101_;
  assign _106_ = r0[5] ? _090_ : _102_;
  assign req_same_tag = r0[5] ? _091_ : _104_;
  assign _107_ = _441_[153:152] == 2'h1;
  assign _108_ = { 30'h00000000, r0[14:13] } == { 30'h00000000, _441_[320:319] };
  assign _109_ = _107_ & _108_;
  assign _110_ = _109_ & req_same_tag;
  assign _111_ = ~ r0[1];
  assign _112_ = 3'h7 - r0[12:10];
  assign _113_ = _111_ | _515_;
  assign _114_ = _110_ ? _113_ : _105_;
  assign req_hit_way = _110_ ? replace_way : _106_;
  assign _115_ = { 27'h0000000, _440_[12:8] } == { 27'h0000000, r0[14:10] };
  assign _116_ = { 31'h00000000, _440_[133] } == { 31'h00000000, req_hit_way };
  assign _117_ = _115_ & _116_;
  assign use_forward1_next = _117_ ? _441_[155] : 1'h0;
  assign _118_ = { 27'h0000000, _441_[142:138] } == { 27'h0000000, r0[14:10] };
  assign _119_ = { 31'h00000000, _441_[137] } == { 31'h00000000, req_hit_way };
  assign _120_ = _118_ & _119_;
  assign use_forward2_next = _120_ ? _441_[136] : 1'h0;
  assign _121_ = 2'h3 - _441_[320:319];
  assign replace_way = _441_[156] ? _516_ : _441_[313];
  assign _122_ = r0[1] | perm_attr[1];
  assign rc_ok = perm_attr[0] & _122_;
  assign _123_ = ~ perm_attr[3];
  assign _124_ = r0[6] | _123_;
  assign _125_ = r0[1] & perm_attr[4];
  assign _126_ = perm_attr[5] | _125_;
  assign perm_ok = _124_ & _126_;
  assign _127_ = valid_ra & perm_ok;
  assign access_ok = _127_ & rc_ok;
  assign _128_ = r0[3] | perm_attr[2];
  assign _129_ = ~ access_ok;
  assign _130_ = { r0[1], _128_, _114_ } == 3'h5;
  assign _131_ = { r0[1], _128_, _114_ } == 3'h4;
  assign _132_ = { r0[1], _128_, _114_ } == 3'h6;
  assign _133_ = { r0[1], _128_, _114_ } == 3'h1;
  assign _134_ = { r0[1], _128_, _114_ } == 3'h0;
  assign _135_ = { r0[1], _128_, _114_ } == 3'h2;
  assign _136_ = { r0[1], _128_, _114_ } == 3'h3;
  assign _137_ = { r0[1], _128_, _114_ } == 3'h7;
  function [2:0] \14813 ;
    input [2:0] a;
    input [23:0] b;
    input [7:0] s;
    (* parallel_case *)
    casez (s)
      8'b???????1:
        \14813  = b[2:0];
      8'b??????1?:
        \14813  = b[5:3];
      8'b?????1??:
        \14813  = b[8:6];
      8'b????1???:
        \14813  = b[11:9];
      8'b???1????:
        \14813  = b[14:12];
      8'b??1?????:
        \14813  = b[17:15];
      8'b?1??????:
        \14813  = b[20:18];
      8'b1???????:
        \14813  = b[23:21];
      default:
        \14813  = a;
    endcase
  endfunction
  assign _138_ = \14813 (3'h0, 24'h27fd63, { _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_ });
  assign _139_ = cancel_store ? 3'h2 : _138_;
  assign _140_ = _129_ ? 3'h1 : _139_;
  assign req_op = req_go ? _140_ : 3'h0;
  assign _141_ = ~ r0_stall;
  assign _142_ = m_in[0] ? m_in[11:7] : d_in[14:10];
  assign early_req_row = _141_ ? _142_ : r0[14:10];
  assign _143_ = r0_valid & r0[4];
  assign _144_ = ~ reservation[0];
  assign _145_ = r0[70:13] != reservation[58:1];
  assign _146_ = _144_ | _145_;
  assign _147_ = _146_ ? 1'h1 : 1'h0;
  assign _148_ = r0[1] ? 1'h0 : _147_;
  assign _149_ = r0[1] ? 1'h1 : 1'h0;
  assign _150_ = r0[1] ? 1'h0 : 1'h1;
  assign cancel_store = _143_ ? _148_ : 1'h0;
  assign set_rsrv = _143_ ? _149_ : 1'h0;
  assign clear_rsrv = _143_ ? _150_ : 1'h0;
  assign _151_ = r0_valid & access_ok;
  assign _152_ = set_rsrv ? { r0[70:13], 1'h1 } : reservation;
  assign _153_ = clear_rsrv ? 1'h0 : _152_[0];
  assign _154_ = clear_rsrv ? reservation[58:1] : _152_[58:1];
  assign _155_ = _151_ ? { _154_, _153_ } : reservation;
  assign _156_ = rst ? 1'h0 : _155_[0];
  assign _157_ = rst ? reservation[58:1] : _155_[58:1];
  always @(posedge clk)
    reservation <= { _157_, _156_ };
  assign _158_ = _441_[143] ? _441_[63:0] : _441_[127:64];
  assign _159_ = 1'h1 - _199_[0];
  assign _160_ = _441_[144] ? _158_[7:0] : _517_[7:0];
  assign _161_ = _441_[145] ? _158_[15:8] : _517_[15:8];
  assign _162_ = _441_[146] ? _158_[23:16] : _517_[23:16];
  assign _163_ = _441_[147] ? _158_[31:24] : _517_[31:24];
  assign _164_ = _441_[148] ? _158_[39:32] : _517_[39:32];
  assign _165_ = _441_[149] ? _158_[47:40] : _517_[47:40];
  assign _166_ = _441_[150] ? _158_[55:48] : _517_[55:48];
  assign _167_ = _441_[151] ? _158_[63:56] : _517_[63:56];
  assign _168_ = ~ _201_[2];
  assign _169_ = 32'd0 == { 31'h00000000, _440_[133] };
  assign _170_ = _169_ ? 1'h1 : 1'h0;
  assign _171_ = _441_[154] ? 64'h0000000000000000 : wishbone_in[63:0];
  assign _172_ = _441_[153:152] == 2'h1;
  assign _173_ = _172_ & wishbone_in[64];
  assign _174_ = { 31'h00000000, replace_way } == 32'd0;
  assign _175_ = _173_ & _174_;
  assign _176_ = _175_ ? 1'h1 : 1'h0;
  assign \rams:0.do_write  = _441_[155] ? _170_ : _176_;
  assign \rams:0.wr_addr  = _441_[155] ? _440_[12:8] : _441_[318:314];
  assign \rams:0.wr_data  = _441_[155] ? _440_[124:61] : _171_;
  assign \rams:0.wr_sel  = _441_[155] ? _440_[132:125] : 8'hff;
  assign \rams:0.wr_sel_m  = \rams:0.do_write  ? \rams:0.wr_sel  : 8'h00;
  assign _177_ = 32'd1 == { 31'h00000000, _440_[133] };
  assign _178_ = _177_ ? 1'h1 : 1'h0;
  assign _179_ = _441_[154] ? 64'h0000000000000000 : wishbone_in[63:0];
  assign _180_ = _441_[153:152] == 2'h1;
  assign _181_ = _180_ & wishbone_in[64];
  assign _182_ = { 31'h00000000, replace_way } == 32'd1;
  assign _183_ = _181_ & _182_;
  assign _184_ = _183_ ? 1'h1 : 1'h0;
  assign \rams:1.do_write  = _441_[155] ? _178_ : _184_;
  assign \rams:1.wr_addr  = _441_[155] ? _440_[12:8] : _441_[318:314];
  assign \rams:1.wr_data  = _441_[155] ? _440_[124:61] : _179_;
  assign \rams:1.wr_sel  = _441_[155] ? _440_[132:125] : 8'hff;
  assign \rams:1.wr_sel_m  = \rams:1.do_write  ? \rams:1.wr_sel  : 8'h00;
  assign _185_ = req_op == 3'h3;
  assign _186_ = _185_ ? 1'h1 : 1'h0;
  assign _187_ = req_op == 3'h3;
  assign _188_ = req_op == 3'h6;
  assign _189_ = _187_ | _188_;
  assign _190_ = _189_ ? 1'h1 : 1'h0;
  assign _191_ = req_op == 3'h1;
  assign _192_ = ~ r0[146];
  assign _193_ = _191_ ? _192_ : 1'h0;
  assign _194_ = _191_ ? { access_ok, r0[146] } : 2'h0;
  assign _195_ = req_op == 3'h2;
  assign _196_ = _195_ ? 1'h1 : 1'h0;
  assign _197_ = r0_valid ? r0[146] : _198_;
  always @(posedge clk)
    _198_ <= _197_;
  always @(posedge clk)
    _199_ <= { r0[20:19], tlb_hit_way, tlb_hit, _190_, r0[14:13], _186_, req_hit_way };
  always @(posedge clk)
    _200_ <= _193_;
  always @(posedge clk)
    _201_ <= { _196_, _194_ };
  assign _202_ = use_forward2_next ? _441_[135:128] : 8'h00;
  assign _203_ = use_forward1_next ? _440_[132:125] : _202_;
  assign _204_ = _441_[154] ? 64'h0000000000000000 : wishbone_in[63:0];
  assign _205_ = _441_[155] ? _440_[124:61] : _204_;
  assign _206_ = r0[143] | r0[145];
  assign _207_ = r0_valid & _206_;
  assign _208_ = req_op == 3'h3;
  assign _209_ = req_op == 3'h2;
  assign _210_ = _208_ | _209_;
  assign _211_ = ~ r0[146];
  assign _212_ = _214_ ? 1'h1 : 1'h0;
  assign _213_ = _211_ ? _207_ : 1'h1;
  assign _214_ = _210_ & _211_;
  assign _215_ = _210_ ? _213_ : _207_;
  assign _216_ = 32'd0 == { 31'h00000000, replace_way };
  assign _217_ = 32'd1 == { 31'h00000000, replace_way };
  assign _218_ = _441_[156] ? 1'h0 : _441_[156];
  assign _219_ = _441_[156] ? replace_way : _441_[313];
  assign _220_ = ~ r0[2];
  assign _221_ = _220_ ? r0[134:71] : 64'h0000000000000000;
  assign _222_ = ~ r0[3];
  assign _223_ = r0[1] & _222_;
  assign _224_ = r0[2] | _223_;
  assign _225_ = _224_ ? 8'hff : r0[142:135];
  assign _226_ = req_op == 3'h4;
  assign _227_ = req_op == 3'h5;
  assign _228_ = _226_ | _227_;
  assign _229_ = req_op == 3'h7;
  assign _230_ = _228_ | _229_;
  assign _231_ = req_op == 3'h6;
  assign _232_ = _230_ | _231_;
  assign _233_ = _232_ ? 1'h1 : _439_;
  assign _234_ = _439_ ? _439_ : _233_;
  assign _235_ = _439_ ? _440_ : { r0[146], req_same_tag, req_hit_way, _225_, _221_, ra, r0[2], req_go, req_op };
  assign _236_ = _235_[10:8] - 3'h1;
  assign _237_ = _235_[2:0] == 3'h6;
  assign _238_ = _237_ ? _235_[133] : _219_;
  assign _239_ = _235_[2:0] == 3'h3;
  assign _240_ = _235_[2:0] == 3'h4;
  assign _241_ = _235_[2:0] == 3'h5;
  assign _242_ = ~ _235_[4];
  assign _243_ = ~ _235_[135];
  assign _244_ = _256_ ? 1'h1 : _212_;
  assign _245_ = _243_ ? _215_ : 1'h1;
  assign _246_ = _235_[2:0] == 3'h6;
  assign _247_ = _252_ ? 1'h1 : 1'h0;
  assign _248_ = _235_[2:0] == 3'h7;
  assign _249_ = _248_ ? 1'h1 : _218_;
  assign _250_ = _242_ ? 1'h0 : _234_;
  assign _251_ = _242_ ? 2'h2 : 2'h1;
  assign _252_ = _242_ & _246_;
  assign _253_ = _242_ ? _218_ : _249_;
  assign _254_ = _242_ ? 1'h1 : 1'h0;
  assign _255_ = _242_ ? 3'h1 : _441_[334:332];
  assign _256_ = _242_ & _243_;
  assign _257_ = _242_ ? _245_ : _215_;
  assign _258_ = _235_[2:0] == 3'h6;
  assign _259_ = _235_[2:0] == 3'h7;
  assign _260_ = _258_ | _259_;
  assign _261_ = _235_[2:0] == 3'h0;
  assign _262_ = _235_[2:0] == 3'h1;
  assign _263_ = _235_[2:0] == 3'h2;
  function [0:0] \15422 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15422  = b[0:0];
      7'b?????1?:
        \15422  = b[1:1];
      7'b????1??:
        \15422  = b[2:2];
      7'b???1???:
        \15422  = b[3:3];
      7'b??1????:
        \15422  = b[4:4];
      7'b?1?????:
        \15422  = b[5:5];
      7'b1??????:
        \15422  = b[6:6];
      default:
        \15422  = a;
    endcase
  endfunction
  assign _264_ = \15422 (1'hx, { _234_, _234_, _234_, _250_, _234_, _234_, _234_ }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [1:0] \15425 ;
    input [1:0] a;
    input [13:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15425  = b[1:0];
      7'b?????1?:
        \15425  = b[3:2];
      7'b????1??:
        \15425  = b[5:4];
      7'b???1???:
        \15425  = b[7:6];
      7'b??1????:
        \15425  = b[9:8];
      7'b?1?????:
        \15425  = b[11:10];
      7'b1??????:
        \15425  = b[13:12];
      default:
        \15425  = a;
    endcase
  endfunction
  assign _265_ = \15425 (2'hx, { _441_[153:152], _441_[153:152], _441_[153:152], _251_, 4'hd, _441_[153:152] }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15427 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15427  = b[0:0];
      7'b?????1?:
        \15427  = b[1:1];
      7'b????1??:
        \15427  = b[2:2];
      7'b???1???:
        \15427  = b[3:3];
      7'b??1????:
        \15427  = b[4:4];
      7'b?1?????:
        \15427  = b[5:5];
      7'b1??????:
        \15427  = b[6:6];
      default:
        \15427  = a;
    endcase
  endfunction
  assign _266_ = \15427 (1'hx, { 3'h0, _247_, 3'h0 }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15429 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15429  = b[0:0];
      7'b?????1?:
        \15429  = b[1:1];
      7'b????1??:
        \15429  = b[2:2];
      7'b???1???:
        \15429  = b[3:3];
      7'b??1????:
        \15429  = b[4:4];
      7'b?1?????:
        \15429  = b[5:5];
      7'b1??????:
        \15429  = b[6:6];
      default:
        \15429  = a;
    endcase
  endfunction
  assign _267_ = \15429 (1'hx, { _218_, _218_, _218_, _253_, _218_, 1'h1, _218_ }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15431 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15431  = b[0:0];
      7'b?????1?:
        \15431  = b[1:1];
      7'b????1??:
        \15431  = b[2:2];
      7'b???1???:
        \15431  = b[3:3];
      7'b??1????:
        \15431  = b[4:4];
      7'b?1?????:
        \15431  = b[5:5];
      7'b1??????:
        \15431  = b[6:6];
      default:
        \15431  = a;
    endcase
  endfunction
  assign _268_ = \15431 (1'hx, { 3'h0, _254_, 3'h0 }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15434 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15434  = b[0:0];
      7'b?????1?:
        \15434  = b[1:1];
      7'b????1??:
        \15434  = b[2:2];
      7'b???1???:
        \15434  = b[3:3];
      7'b??1????:
        \15434  = b[4:4];
      7'b?1?????:
        \15434  = b[5:5];
      7'b1??????:
        \15434  = b[6:6];
      default:
        \15434  = a;
    endcase
  endfunction
  assign _269_ = \15434 (1'hx, { _441_[254], _441_[254], _441_[254], 3'h7, _441_[254] }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15437 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15437  = b[0:0];
      7'b?????1?:
        \15437  = b[1:1];
      7'b????1??:
        \15437  = b[2:2];
      7'b???1???:
        \15437  = b[3:3];
      7'b??1????:
        \15437  = b[4:4];
      7'b?1?????:
        \15437  = b[5:5];
      7'b1??????:
        \15437  = b[6:6];
      default:
        \15437  = a;
    endcase
  endfunction
  assign _270_ = \15437 (1'hx, { _441_[255], _441_[255], _441_[255], 3'h7, _441_[255] }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15440 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15440  = b[0:0];
      7'b?????1?:
        \15440  = b[1:1];
      7'b????1??:
        \15440  = b[2:2];
      7'b???1???:
        \15440  = b[3:3];
      7'b??1????:
        \15440  = b[4:4];
      7'b?1?????:
        \15440  = b[5:5];
      7'b1??????:
        \15440  = b[6:6];
      default:
        \15440  = a;
    endcase
  endfunction
  assign _271_ = \15440 (1'hx, { _441_[264], _441_[264], _441_[264], 3'h4, _441_[264] }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [2:0] \15443 ;
    input [2:0] a;
    input [20:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15443  = b[2:0];
      7'b?????1?:
        \15443  = b[5:3];
      7'b????1??:
        \15443  = b[8:6];
      7'b???1???:
        \15443  = b[11:9];
      7'b??1????:
        \15443  = b[14:12];
      7'b?1?????:
        \15443  = b[17:15];
      7'b1??????:
        \15443  = b[20:18];
      default:
        \15443  = a;
    endcase
  endfunction
  assign _272_ = \15443 (3'hx, { _441_[334:332], _441_[334:332], _441_[334:332], _255_, _441_[334:332], _441_[334:332], _441_[334:332] }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15445 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15445  = b[0:0];
      7'b?????1?:
        \15445  = b[1:1];
      7'b????1??:
        \15445  = b[2:2];
      7'b???1???:
        \15445  = b[3:3];
      7'b??1????:
        \15445  = b[4:4];
      7'b?1?????:
        \15445  = b[5:5];
      7'b1??????:
        \15445  = b[6:6];
      default:
        \15445  = a;
    endcase
  endfunction
  assign _273_ = \15445 (1'hx, { _212_, _212_, _212_, _244_, _212_, _212_, _212_ }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  function [0:0] \15447 ;
    input [0:0] a;
    input [6:0] b;
    input [6:0] s;
    (* parallel_case *)
    casez (s)
      7'b??????1:
        \15447  = b[0:0];
      7'b?????1?:
        \15447  = b[1:1];
      7'b????1??:
        \15447  = b[2:2];
      7'b???1???:
        \15447  = b[3:3];
      7'b??1????:
        \15447  = b[4:4];
      7'b?1?????:
        \15447  = b[5:5];
      7'b1??????:
        \15447  = b[6:6];
      default:
        \15447  = a;
    endcase
  endfunction
  assign _274_ = \15447 (1'hx, { _215_, _215_, _215_, _257_, _215_, _215_, _215_ }, { _263_, _262_, _261_, _260_, _241_, _240_, _239_ });
  assign _275_ = _441_[153:152] == 2'h0;
  assign _276_ = ~ _441_[255];
  assign _277_ = ~ wishbone_in[65];
  assign _278_ = ~ _276_;
  assign _279_ = _277_ & _278_;
  assign _280_ = _441_[163:161] == _441_[323:321];
  assign _281_ = _285_ ? 1'h0 : _441_[255];
  assign _282_ = _286_ ? 1'h1 : _276_;
  assign _283_ = _441_[163:161] + 3'h1;
  assign _284_ = _279_ ? { _441_[189:164], _283_, _441_[160:158] } : _441_[189:158];
  assign _285_ = _279_ & _280_;
  assign _286_ = _279_ & _280_;
  assign _287_ = 3'h7 - _441_[316:314];
  assign _288_ = _439_ & _440_[134];
  assign _289_ = _441_[154] & _440_[4];
  assign _290_ = ~ _441_[154];
  assign _291_ = _440_[2:0] == 3'h4;
  assign _292_ = _290_ & _291_;
  assign _293_ = _289_ | _292_;
  assign _294_ = _288_ & _293_;
  assign _295_ = { 27'h0000000, _441_[318:314] } == { 27'h0000000, _440_[12:8] };
  assign _296_ = _294_ & _295_;
  assign _297_ = ~ _198_;
  assign _298_ = _319_ ? 1'h1 : _212_;
  assign _299_ = _297_ ? _215_ : 1'h1;
  assign _300_ = _313_ ? 1'h0 : _234_;
  assign _301_ = _296_ ? 9'h1ff : { _203_, use_forward1_next };
  assign _302_ = _315_ ? 1'h1 : 1'h0;
  assign _303_ = _296_ & _297_;
  assign _304_ = _320_ ? _299_ : _215_;
  assign _305_ = _441_[316:314] == _441_[323:321];
  assign _306_ = _282_ & _305_;
  assign _307_ = 2'h3 - _441_[320:319];
  assign _308_ = _312_ ? { _563_, _562_, _561_, _560_, _559_, _558_, _557_, _556_ } : cache_valids;
  assign _309_ = _306_ ? 2'h0 : _441_[153:152];
  assign _310_ = _316_ ? 1'h0 : _441_[254];
  assign _311_ = _441_[316:314] + 3'h1;
  assign _312_ = wishbone_in[64] & _306_;
  assign _313_ = wishbone_in[64] & _296_;
  assign _314_ = wishbone_in[64] ? { _309_, _301_ } : { _441_[153:152], _203_, use_forward1_next };
  assign _315_ = wishbone_in[64] & _296_;
  assign _316_ = wishbone_in[64] & _306_;
  assign _317_ = wishbone_in[64] ? { _441_[318:317], _311_ } : _441_[318:314];
  assign _318_ = wishbone_in[64] ? { _540_, _539_, _538_, _537_, _536_, _535_, _534_, _533_ } : _441_[331:324];
  assign _319_ = wishbone_in[64] & _303_;
  assign _320_ = wishbone_in[64] & _296_;
  assign _321_ = _441_[153:152] == 2'h1;
  assign _322_ = ~ _441_[255];
  assign _323_ = _441_[335] != _441_[336];
  assign _324_ = _441_[334:332] + 3'h1;
  assign _325_ = _441_[334:332] - 3'h1;
  assign _326_ = _441_[335] ? _324_ : _325_;
  assign _327_ = _323_ ? _326_ : _441_[334:332];
  assign _328_ = ~ wishbone_in[65];
  assign _329_ = _235_[3] ? _235_[12:5] : _441_[165:158];
  assign _330_ = _350_ ? _235_[124:61] : _441_[253:190];
  assign _331_ = _235_[3] ? _235_[132:125] : _441_[263:256];
  assign _332_ = _327_ < 3'h7;
  assign _333_ = _332_ & _235_[134];
  assign _334_ = _235_[2:0] == 3'h7;
  assign _335_ = _235_[2:0] == 3'h6;
  assign _336_ = _334_ | _335_;
  assign _337_ = _333_ & _336_;
  assign _338_ = _235_[2:0] == 3'h6;
  assign _339_ = _348_ ? 1'h1 : 1'h0;
  assign _340_ = _347_ ? 1'h0 : _234_;
  assign _341_ = _337_ & _338_;
  assign _342_ = _337_ ? 1'h1 : 1'h0;
  assign _343_ = _337_ ? 1'h1 : 1'h0;
  assign _344_ = _351_ ? 1'h1 : 1'h0;
  assign _345_ = _352_ ? 1'h1 : _212_;
  assign _346_ = _337_ ? 1'h0 : 1'h1;
  assign _347_ = _328_ & _337_;
  assign _348_ = _328_ & _341_;
  assign _349_ = _328_ ? { _329_, _342_ } : { _441_[165:158], 1'h0 };
  assign _350_ = _328_ & _235_[3];
  assign _351_ = _328_ & _337_;
  assign _352_ = _328_ & _337_;
  assign _353_ = _328_ ? _346_ : _322_;
  assign _354_ = _327_ == 3'h1;
  assign _355_ = _353_ & _354_;
  assign _356_ = _359_ ? 2'h0 : _441_[153:152];
  assign _357_ = _328_ ? _343_ : _441_[255];
  assign _358_ = _355_ ? 2'h0 : { _357_, _441_[254] };
  assign _359_ = wishbone_in[64] & _355_;
  assign _360_ = _328_ ? _343_ : _441_[255];
  assign _361_ = wishbone_in[64] ? _358_ : { _360_, _441_[254] };
  assign _362_ = wishbone_in[64] ? 1'h1 : 1'h0;
  assign _363_ = _328_ ? _331_ : _441_[263:256];
  assign _364_ = _441_[153:152] == 2'h2;
  assign _365_ = ~ wishbone_in[65];
  assign _366_ = _365_ ? 1'h0 : _441_[255];
  assign _367_ = ~ _198_;
  assign _368_ = _374_ ? 1'h1 : _212_;
  assign _369_ = _367_ ? _215_ : 1'h1;
  assign _370_ = wishbone_in[64] ? 1'h0 : _234_;
  assign _371_ = wishbone_in[64] ? 11'h1ff : { _441_[153:152], _203_, use_forward1_next };
  assign _372_ = wishbone_in[64] ? 1'h1 : 1'h0;
  assign _373_ = wishbone_in[64] ? 2'h0 : { _366_, _441_[254] };
  assign _374_ = wishbone_in[64] & _367_;
  assign _375_ = wishbone_in[64] ? _369_ : _215_;
  assign _376_ = _441_[153:152] == 2'h3;
  function [7:0] \15761 ;
    input [7:0] a;
    input [31:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15761  = b[7:0];
      4'b??1?:
        \15761  = b[15:8];
      4'b?1??:
        \15761  = b[23:16];
      4'b1???:
        \15761  = b[31:24];
      default:
        \15761  = a;
    endcase
  endfunction
  assign _377_ = \15761 (8'hxx, { cache_valids, cache_valids, _308_, cache_valids }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15763 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15763  = b[0:0];
      4'b??1?:
        \15763  = b[1:1];
      4'b?1??:
        \15763  = b[2:2];
      4'b1???:
        \15763  = b[3:3];
      default:
        \15763  = a;
    endcase
  endfunction
  assign _378_ = \15763 (1'hx, { _370_, _340_, _300_, _264_ }, { _376_, _364_, _321_, _275_ });
  assign _379_ = _232_ ? req_same_tag : _440_[134];
  assign _380_ = _439_ ? _440_[134] : _379_;
  function [0:0] \15770 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15770  = b[0:0];
      4'b??1?:
        \15770  = b[1:1];
      4'b?1??:
        \15770  = b[2:2];
      4'b1???:
        \15770  = b[3:3];
      default:
        \15770  = a;
    endcase
  endfunction
  assign _381_ = \15770 (1'hx, { _380_, _380_, _380_, 1'h1 }, { _376_, _364_, _321_, _275_ });
  assign _382_ = _441_[155] ? 1'h1 : 1'h0;
  function [0:0] \15775 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15775  = b[0:0];
      4'b??1?:
        \15775  = b[1:1];
      4'b?1??:
        \15775  = b[2:2];
      4'b1???:
        \15775  = b[3:3];
      default:
        \15775  = a;
    endcase
  endfunction
  assign _383_ = \15775 (1'hx, { _382_, _382_, wishbone_in[64], _382_ }, { _376_, _364_, _321_, _275_ });
  function [8:0] \15780 ;
    input [8:0] a;
    input [35:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15780  = b[8:0];
      4'b??1?:
        \15780  = b[17:9];
      4'b?1??:
        \15780  = b[26:18];
      4'b1???:
        \15780  = b[35:27];
      default:
        \15780  = a;
    endcase
  endfunction
  assign _384_ = \15780 (9'hxxx, { _371_[8:0], _203_, use_forward1_next, _314_[8:0], _203_, use_forward1_next }, { _376_, _364_, _321_, _275_ });
  function [1:0] \15784 ;
    input [1:0] a;
    input [7:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15784  = b[1:0];
      4'b??1?:
        \15784  = b[3:2];
      4'b?1??:
        \15784  = b[5:4];
      4'b1???:
        \15784  = b[7:6];
      default:
        \15784  = a;
    endcase
  endfunction
  assign _385_ = \15784 (2'hx, { _371_[10:9], _356_, _314_[10:9], _265_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15787 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15787  = b[0:0];
      4'b??1?:
        \15787  = b[1:1];
      4'b?1??:
        \15787  = b[2:2];
      4'b1???:
        \15787  = b[3:3];
      default:
        \15787  = a;
    endcase
  endfunction
  assign _386_ = \15787 (1'hx, { _441_[154], _441_[154], _441_[154], _235_[4] }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15789 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15789  = b[0:0];
      4'b??1?:
        \15789  = b[1:1];
      4'b?1??:
        \15789  = b[2:2];
      4'b1???:
        \15789  = b[3:3];
      default:
        \15789  = a;
    endcase
  endfunction
  assign _387_ = \15789 (1'hx, { 1'h0, _339_, 1'h0, _266_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15791 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15791  = b[0:0];
      4'b??1?:
        \15791  = b[1:1];
      4'b?1??:
        \15791  = b[2:2];
      4'b1???:
        \15791  = b[3:3];
      default:
        \15791  = a;
    endcase
  endfunction
  assign _388_ = \15791 (1'hx, { _218_, _218_, _218_, _267_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15794 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15794  = b[0:0];
      4'b??1?:
        \15794  = b[1:1];
      4'b?1??:
        \15794  = b[2:2];
      4'b1???:
        \15794  = b[3:3];
      default:
        \15794  = a;
    endcase
  endfunction
  assign _389_ = \15794 (1'hx, { _372_, _349_[0], _302_, _268_ }, { _376_, _364_, _321_, _275_ });
  function [7:0] \15800 ;
    input [7:0] a;
    input [31:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15800  = b[7:0];
      4'b??1?:
        \15800  = b[15:8];
      4'b?1??:
        \15800  = b[23:16];
      4'b1???:
        \15800  = b[31:24];
      default:
        \15800  = a;
    endcase
  endfunction
  assign _390_ = \15800 (8'hxx, { _441_[165:158], _349_[8:1], _284_[7:0], _235_[12:5] }, { _376_, _364_, _321_, _275_ });
  function [23:0] \15805 ;
    input [23:0] a;
    input [95:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15805  = b[23:0];
      4'b??1?:
        \15805  = b[47:24];
      4'b?1??:
        \15805  = b[71:48];
      4'b1???:
        \15805  = b[95:72];
      default:
        \15805  = a;
    endcase
  endfunction
  assign _391_ = \15805 (24'hxxxxxx, { _441_[189:166], _441_[189:166], _284_[31:8], _235_[36:13] }, { _376_, _364_, _321_, _275_ });
  function [63:0] \15808 ;
    input [63:0] a;
    input [255:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15808  = b[63:0];
      4'b??1?:
        \15808  = b[127:64];
      4'b?1??:
        \15808  = b[191:128];
      4'b1???:
        \15808  = b[255:192];
      default:
        \15808  = a;
    endcase
  endfunction
  assign _392_ = \15808 (64'hxxxxxxxxxxxxxxxx, { _441_[253:190], _330_, _441_[253:190], _235_[124:61] }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15812 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15812  = b[0:0];
      4'b??1?:
        \15812  = b[1:1];
      4'b?1??:
        \15812  = b[2:2];
      4'b1???:
        \15812  = b[3:3];
      default:
        \15812  = a;
    endcase
  endfunction
  assign _393_ = \15812 (1'hx, { _373_[0], _361_[0], _310_, _269_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15816 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15816  = b[0:0];
      4'b??1?:
        \15816  = b[1:1];
      4'b?1??:
        \15816  = b[2:2];
      4'b1???:
        \15816  = b[3:3];
      default:
        \15816  = a;
    endcase
  endfunction
  assign _394_ = \15816 (1'hx, { _373_[1], _361_[1], _281_, _270_ }, { _376_, _364_, _321_, _275_ });
  function [7:0] \15819 ;
    input [7:0] a;
    input [31:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15819  = b[7:0];
      4'b??1?:
        \15819  = b[15:8];
      4'b?1??:
        \15819  = b[23:16];
      4'b1???:
        \15819  = b[31:24];
      default:
        \15819  = a;
    endcase
  endfunction
  assign _395_ = \15819 (8'hxx, { _441_[263:256], _363_, _441_[263:256], _235_[132:125] }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15822 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15822  = b[0:0];
      4'b??1?:
        \15822  = b[1:1];
      4'b?1??:
        \15822  = b[2:2];
      4'b1???:
        \15822  = b[3:3];
      default:
        \15822  = a;
    endcase
  endfunction
  assign _396_ = \15822 (1'hx, { _441_[264], _441_[264], _441_[264], _271_ }, { _376_, _364_, _321_, _275_ });
  function [47:0] \15825 ;
    input [47:0] a;
    input [191:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15825  = b[47:0];
      4'b??1?:
        \15825  = b[95:48];
      4'b?1??:
        \15825  = b[143:96];
      4'b1???:
        \15825  = b[191:144];
      default:
        \15825  = a;
    endcase
  endfunction
  assign _397_ = \15825 (48'hxxxxxxxxxxxx, { _441_[312:265], _441_[312:265], _441_[312:265], _235_[60:13] }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15827 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15827  = b[0:0];
      4'b??1?:
        \15827  = b[1:1];
      4'b?1??:
        \15827  = b[2:2];
      4'b1???:
        \15827  = b[3:3];
      default:
        \15827  = a;
    endcase
  endfunction
  assign _398_ = \15827 (1'hx, { _219_, _219_, _219_, _238_ }, { _376_, _364_, _321_, _275_ });
  function [4:0] \15830 ;
    input [4:0] a;
    input [19:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15830  = b[4:0];
      4'b??1?:
        \15830  = b[9:5];
      4'b?1??:
        \15830  = b[14:10];
      4'b1???:
        \15830  = b[19:15];
      default:
        \15830  = a;
    endcase
  endfunction
  assign _399_ = \15830 (5'hxx, { _441_[318:314], _441_[318:314], _317_, _235_[12:8] }, { _376_, _364_, _321_, _275_ });
  function [1:0] \15833 ;
    input [1:0] a;
    input [7:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15833  = b[1:0];
      4'b??1?:
        \15833  = b[3:2];
      4'b?1??:
        \15833  = b[5:4];
      4'b1???:
        \15833  = b[7:6];
      default:
        \15833  = a;
    endcase
  endfunction
  assign _400_ = \15833 (2'hx, { _441_[320:319], _441_[320:319], _441_[320:319], _235_[12:11] }, { _376_, _364_, _321_, _275_ });
  function [2:0] \15836 ;
    input [2:0] a;
    input [11:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15836  = b[2:0];
      4'b??1?:
        \15836  = b[5:3];
      4'b?1??:
        \15836  = b[8:6];
      4'b1???:
        \15836  = b[11:9];
      default:
        \15836  = a;
    endcase
  endfunction
  assign _401_ = \15836 (3'hx, { _441_[323:321], _441_[323:321], _441_[323:321], _236_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15840 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15840  = b[0:0];
      4'b??1?:
        \15840  = b[1:1];
      4'b?1??:
        \15840  = b[2:2];
      4'b1???:
        \15840  = b[3:3];
      default:
        \15840  = a;
    endcase
  endfunction
  assign _402_ = \15840 (1'hx, { _441_[324], _441_[324], _318_[0], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15844 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15844  = b[0:0];
      4'b??1?:
        \15844  = b[1:1];
      4'b?1??:
        \15844  = b[2:2];
      4'b1???:
        \15844  = b[3:3];
      default:
        \15844  = a;
    endcase
  endfunction
  assign _403_ = \15844 (1'hx, { _441_[325], _441_[325], _318_[1], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15848 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15848  = b[0:0];
      4'b??1?:
        \15848  = b[1:1];
      4'b?1??:
        \15848  = b[2:2];
      4'b1???:
        \15848  = b[3:3];
      default:
        \15848  = a;
    endcase
  endfunction
  assign _404_ = \15848 (1'hx, { _441_[326], _441_[326], _318_[2], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15852 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15852  = b[0:0];
      4'b??1?:
        \15852  = b[1:1];
      4'b?1??:
        \15852  = b[2:2];
      4'b1???:
        \15852  = b[3:3];
      default:
        \15852  = a;
    endcase
  endfunction
  assign _405_ = \15852 (1'hx, { _441_[327], _441_[327], _318_[3], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15856 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15856  = b[0:0];
      4'b??1?:
        \15856  = b[1:1];
      4'b?1??:
        \15856  = b[2:2];
      4'b1???:
        \15856  = b[3:3];
      default:
        \15856  = a;
    endcase
  endfunction
  assign _406_ = \15856 (1'hx, { _441_[328], _441_[328], _318_[4], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15860 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15860  = b[0:0];
      4'b??1?:
        \15860  = b[1:1];
      4'b?1??:
        \15860  = b[2:2];
      4'b1???:
        \15860  = b[3:3];
      default:
        \15860  = a;
    endcase
  endfunction
  assign _407_ = \15860 (1'hx, { _441_[329], _441_[329], _318_[5], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15864 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15864  = b[0:0];
      4'b??1?:
        \15864  = b[1:1];
      4'b?1??:
        \15864  = b[2:2];
      4'b1???:
        \15864  = b[3:3];
      default:
        \15864  = a;
    endcase
  endfunction
  assign _408_ = \15864 (1'hx, { _441_[330], _441_[330], _318_[6], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15868 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15868  = b[0:0];
      4'b??1?:
        \15868  = b[1:1];
      4'b?1??:
        \15868  = b[2:2];
      4'b1???:
        \15868  = b[3:3];
      default:
        \15868  = a;
    endcase
  endfunction
  assign _409_ = \15868 (1'hx, { _441_[331], _441_[331], _318_[7], 1'h0 }, { _376_, _364_, _321_, _275_ });
  function [2:0] \15871 ;
    input [2:0] a;
    input [11:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15871  = b[2:0];
      4'b??1?:
        \15871  = b[5:3];
      4'b?1??:
        \15871  = b[8:6];
      4'b1???:
        \15871  = b[11:9];
      default:
        \15871  = a;
    endcase
  endfunction
  assign _410_ = \15871 (3'hx, { _441_[334:332], _327_, _441_[334:332], _272_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15873 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15873  = b[0:0];
      4'b??1?:
        \15873  = b[1:1];
      4'b?1??:
        \15873  = b[2:2];
      4'b1???:
        \15873  = b[3:3];
      default:
        \15873  = a;
    endcase
  endfunction
  assign _411_ = \15873 (1'hx, { 1'h0, _344_, 2'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15875 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15875  = b[0:0];
      4'b??1?:
        \15875  = b[1:1];
      4'b?1??:
        \15875  = b[2:2];
      4'b1???:
        \15875  = b[3:3];
      default:
        \15875  = a;
    endcase
  endfunction
  assign _412_ = \15875 (1'hx, { 1'h0, _362_, 2'h0 }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15877 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15877  = b[0:0];
      4'b??1?:
        \15877  = b[1:1];
      4'b?1??:
        \15877  = b[2:2];
      4'b1???:
        \15877  = b[3:3];
      default:
        \15877  = a;
    endcase
  endfunction
  assign _413_ = \15877 (1'hx, { _368_, _345_, _298_, _273_ }, { _376_, _364_, _321_, _275_ });
  function [0:0] \15879 ;
    input [0:0] a;
    input [3:0] b;
    input [3:0] s;
    (* parallel_case *)
    casez (s)
      4'b???1:
        \15879  = b[0:0];
      4'b??1?:
        \15879  = b[1:1];
      4'b?1??:
        \15879  = b[2:2];
      4'b1???:
        \15879  = b[3:3];
      default:
        \15879  = a;
    endcase
  endfunction
  assign _414_ = \15879 (1'hx, { _375_, _215_, _304_, _274_ }, { _376_, _364_, _321_, _275_ });
  assign _415_ = _232_ ? r0[146] : _440_[135];
  assign _416_ = _439_ ? _440_[135] : _415_;
  assign _417_ = _232_ ? { req_hit_way, _225_, _221_, ra, r0[2], req_go, req_op } : _440_[133:0];
  assign _418_ = _439_ ? _440_[133:0] : _417_;
  assign _419_ = rst ? 8'h00 : _377_;
  assign _420_ = rst ? 1'h0 : _378_;
  assign _421_ = rst ? _440_ : { _416_, _381_, _418_ };
  assign _422_ = _441_[155] ? 1'h1 : 1'h0;
  assign _423_ = rst ? _422_ : _383_;
  assign _424_ = rst ? { _203_, use_forward1_next } : _384_;
  assign _425_ = rst ? 2'h0 : _385_;
  assign _426_ = rst ? _441_[156:154] : { _388_, _387_, _386_ };
  assign _427_ = rst ? 33'h000000000 : { _391_, _390_, _389_ };
  assign _428_ = rst ? _441_[253:190] : _392_;
  assign _429_ = rst ? 2'h0 : { _394_, _393_ };
  assign _430_ = rst ? _441_[336:256] : { _412_, _411_, _410_, _409_, _408_, _407_, _406_, _405_, _404_, _403_, _402_, _401_, _400_, _399_, _398_, _397_, _396_, _395_ };
  assign _431_ = rst ? 1'h0 : _413_;
  assign _432_ = rst ? 1'h0 : _414_;
  assign _433_ = _441_[155] ? { _440_[12:8], _440_[133] } : { _441_[318:314], replace_way };
  assign _434_ = _441_[155] ? _440_[132:125] : 8'hff;
  assign _435_ = ~ rst;
  assign _436_ = _435_ & _441_[156];
  assign _437_ = _436_ & _217_;
  assign _438_ = _436_ & _216_;
  always @(posedge clk)
    cache_valids <= _419_;
  always @(posedge clk)
    _439_ <= _420_;
  always @(posedge clk)
    _440_ <= _421_;
  always @(posedge clk)
    _441_ <= { _431_, _430_, _429_, _428_, _427_, _426_, _425_, _424_, _433_, _423_, _434_, _441_[63:0], _205_ };
  always @(posedge clk)
    _442_ <= _432_;
  always @(posedge clk)
    \dc_log.log_data  <= { _441_[163:161], wishbone_in[65:64], _441_[255:254], _200_, _441_[337], req_op, r0_stall, 2'h0, tlb_hit_way, valid_ra, 1'h0, _441_[153:152] };
  assign _450_ = tlb_hit_way ? tlb_pte_way[127:64] : tlb_pte_way[63:0];
  assign _451_ = ~ _030_[1];
  assign _452_ = ~ _030_[0];
  assign _453_ = _451_ & _452_;
  assign _454_ = _451_ & _030_[0];
  assign _455_ = _030_[1] & _452_;
  assign _456_ = _030_[1] & _030_[0];
  assign _457_ = ~ tlb_hit_way;
  assign _458_ = _453_ & _457_;
  assign _459_ = _453_ & tlb_hit_way;
  assign _460_ = _454_ & _457_;
  assign _461_ = _454_ & tlb_hit_way;
  assign _462_ = _455_ & _457_;
  assign _463_ = _455_ & tlb_hit_way;
  assign _464_ = _456_ & _457_;
  assign _465_ = _456_ & tlb_hit_way;
  assign _466_ = _458_ ? 1'h0 : dtlb_valids[0];
  assign _467_ = _459_ ? 1'h0 : dtlb_valids[1];
  assign _468_ = _460_ ? 1'h0 : dtlb_valids[2];
  assign _469_ = _461_ ? 1'h0 : dtlb_valids[3];
  assign _470_ = _462_ ? 1'h0 : dtlb_valids[4];
  assign _471_ = _463_ ? 1'h0 : dtlb_valids[5];
  assign _472_ = _464_ ? 1'h0 : dtlb_valids[6];
  assign _473_ = _465_ ? 1'h0 : dtlb_valids[7];
  assign _475_ = ~ _033_;
  assign _476_ = _475_ ? r0[70:21] : tlb_tag_way[49:0];
  assign _477_ = _033_ ? r0[70:21] : tlb_tag_way[99:50];
  assign _478_ = ~ _033_;
  assign _479_ = _478_ ? r0[134:71] : tlb_pte_way[63:0];
  assign _480_ = _033_ ? r0[134:71] : tlb_pte_way[127:64];
  assign _481_ = ~ _034_[1];
  assign _482_ = ~ _034_[0];
  assign _483_ = _481_ & _482_;
  assign _484_ = _481_ & _034_[0];
  assign _485_ = _034_[1] & _482_;
  assign _486_ = _034_[1] & _034_[0];
  assign _487_ = ~ _033_;
  assign _488_ = _483_ & _487_;
  assign _489_ = _483_ & _033_;
  assign _490_ = _484_ & _487_;
  assign _491_ = _484_ & _033_;
  assign _492_ = _485_ & _487_;
  assign _493_ = _485_ & _033_;
  assign _494_ = _486_ & _487_;
  assign _495_ = _486_ & _033_;
  assign _496_ = _488_ ? 1'h1 : dtlb_valids[0];
  assign _497_ = _489_ ? 1'h1 : dtlb_valids[1];
  assign _498_ = _490_ ? 1'h1 : dtlb_valids[2];
  assign _499_ = _491_ ? 1'h1 : dtlb_valids[3];
  assign _500_ = _492_ ? 1'h1 : dtlb_valids[4];
  assign _501_ = _493_ ? 1'h1 : dtlb_valids[5];
  assign _502_ = _494_ ? 1'h1 : dtlb_valids[6];
  assign _503_ = _495_ ? 1'h1 : dtlb_valids[7];
  assign _508_ = tlb_hit_way ? _084_ : _068_;
  assign _509_ = _088_ ? _069_ : _085_;
  assign _510_ = tlb_hit_way ? _087_ : _071_;
  assign _515_ = _112_[2] ? _514_ : _513_;
  assign _517_ = _159_ ? \rams:0.dout  : \rams:1.dout ;
  assign _518_ = ~ _287_[2];
  assign _519_ = ~ _287_[1];
  assign _520_ = _518_ & _519_;
  assign _521_ = _518_ & _287_[1];
  assign _522_ = _287_[2] & _519_;
  assign _523_ = _287_[2] & _287_[1];
  assign _524_ = ~ _287_[0];
  assign _525_ = _520_ & _524_;
  assign _526_ = _520_ & _287_[0];
  assign _527_ = _521_ & _524_;
  assign _528_ = _521_ & _287_[0];
  assign _529_ = _522_ & _524_;
  assign _530_ = _522_ & _287_[0];
  assign _531_ = _523_ & _524_;
  assign _532_ = _523_ & _287_[0];
  assign _533_ = _525_ ? 1'h1 : _441_[324];
  assign _534_ = _526_ ? 1'h1 : _441_[325];
  assign _535_ = _527_ ? 1'h1 : _441_[326];
  assign _536_ = _528_ ? 1'h1 : _441_[327];
  assign _537_ = _529_ ? 1'h1 : _441_[328];
  assign _538_ = _530_ ? 1'h1 : _441_[329];
  assign _539_ = _531_ ? 1'h1 : _441_[330];
  assign _540_ = _532_ ? 1'h1 : _441_[331];
  assign _541_ = ~ _307_[1];
  assign _542_ = ~ _307_[0];
  assign _543_ = _541_ & _542_;
  assign _544_ = _541_ & _307_[0];
  assign _545_ = _307_[1] & _542_;
  assign _546_ = _307_[1] & _307_[0];
  assign _547_ = ~ _441_[313];
  assign _548_ = _543_ & _547_;
  assign _549_ = _543_ & _441_[313];
  assign _550_ = _544_ & _547_;
  assign _551_ = _544_ & _441_[313];
  assign _552_ = _545_ & _547_;
  assign _553_ = _545_ & _441_[313];
  assign _554_ = _546_ & _547_;
  assign _555_ = _546_ & _441_[313];
  assign _556_ = _548_ ? 1'h1 : cache_valids[0];
  assign _557_ = _549_ ? 1'h1 : cache_valids[1];
  assign _558_ = _550_ ? 1'h1 : cache_valids[2];
  assign _559_ = _551_ ? 1'h1 : cache_valids[3];
  assign _560_ = _552_ ? 1'h1 : cache_valids[4];
  assign _561_ = _553_ ? 1'h1 : cache_valids[5];
  assign _562_ = _554_ ? 1'h1 : cache_valids[6];
  assign _563_ = _555_ ? 1'h1 : cache_valids[7];
  plru_1 \maybe_plrus.plrus:0.plru  (
    .acc(_199_[0]),
    .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:0.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:1.plru  (
    .acc(_199_[0]),
    .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:1.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:2.plru  (
    .acc(_199_[0]),
    .acc_en(\maybe_plrus.plrus:2.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:2.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_plrus.plrus:3.plru  (
    .acc(_199_[0]),
    .acc_en(\maybe_plrus.plrus:3.plru_acc_en ),
    .clk(clk),
    .lru(\maybe_plrus.plrus:3.plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_tlb_plrus.tlb_plrus:0.tlb_plru  (
    .acc(_199_[6]),
    .acc_en(\maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en ),
    .clk(clk),
    .lru(\maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_tlb_plrus.tlb_plrus:1.tlb_plru  (
    .acc(_199_[6]),
    .acc_en(\maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en ),
    .clk(clk),
    .lru(\maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_tlb_plrus.tlb_plrus:2.tlb_plru  (
    .acc(_199_[6]),
    .acc_en(\maybe_tlb_plrus.tlb_plrus:2.tlb_plru_acc_en ),
    .clk(clk),
    .lru(\maybe_tlb_plrus.tlb_plrus:2.tlb_plru_out ),
    .rst(rst)
  );
  plru_1 \maybe_tlb_plrus.tlb_plrus:3.tlb_plru  (
    .acc(_199_[6]),
    .acc_en(\maybe_tlb_plrus.tlb_plrus:3.tlb_plru_acc_en ),
    .clk(clk),
    .lru(\maybe_tlb_plrus.tlb_plrus:3.tlb_plru_out ),
    .rst(rst)
  );
  cache_ram_5_64_3f29546453678b855931c174a97d6c0894b8f546 \rams:0.way  (
    .clk(clk),
    .rd_addr(early_req_row),
    .rd_data(\rams:0.dout ),
    .rd_en(1'h1),
    .wr_addr(\rams:0.wr_addr ),
    .wr_data(\rams:0.wr_data ),
    .wr_sel(\rams:0.wr_sel_m )
  );
  cache_ram_5_64_3f29546453678b855931c174a97d6c0894b8f546 \rams:1.way  (
    .clk(clk),
    .rd_addr(early_req_row),
    .rd_data(\rams:1.dout ),
    .rd_en(1'h1),
    .wr_addr(\rams:1.wr_addr ),
    .wr_data(\rams:1.wr_data ),
    .wr_sel(\rams:1.wr_sel_m )
  );
  assign d_out = { _201_[1], _200_, _168_, _167_, _166_, _165_, _164_, _163_, _162_, _161_, _160_, _441_[337] };
  assign m_out = { _167_, _166_, _165_, _164_, _163_, _162_, _161_, _160_, _201_[0], _442_, 1'h0 };
  assign stall_out = r0_stall;
  assign wishbone_out = _441_[264:158];
  assign log_out = \dc_log.log_data ;
endmodule

module cache_ram_5_64_3f29546453678b855931c174a97d6c0894b8f546(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
  reg [63:0] _00_;
  wire [255:0] _01_;
  wire [7:0] _02_;
  wire [255:0] _03_;
  wire [7:0] _04_;
  wire [255:0] _05_;
  wire [7:0] _06_;
  wire [255:0] _07_;
  wire [7:0] _08_;
  wire [255:0] _09_;
  wire [7:0] _10_;
  wire [255:0] _11_;
  wire [7:0] _12_;
  wire [255:0] _13_;
  wire [7:0] _14_;
  wire [255:0] _15_;
  wire [7:0] _16_;
  input clk;
  input [4:0] rd_addr;
  output [63:0] rd_data;
  input rd_en;
  input [4:0] wr_addr;
  input [63:0] wr_data;
  input [7:0] wr_sel;
  reg [7:0] \$mem$\22359  [31:0];
  reg [7:0] \$mem$\22360  [31:0];
  reg [7:0] \$mem$\22361  [31:0];
  reg [7:0] \$mem$\22362  [31:0];
  reg [7:0] \$mem$\22363  [31:0];
  reg [7:0] \$mem$\22364  [31:0];
  reg [7:0] \$mem$\22365  [31:0];
  reg [7:0] \$mem$\22366  [31:0];
  (* ram_style = "block" *)
  reg [7:0] \22359  [31:0];
  reg [7:0] _17_;
  always @(posedge clk) begin
    if (rd_en) _17_ <= \22359 [rd_addr];
    if (wr_sel[0]) \22359 [wr_addr] <= wr_data[7:0];
  end
  assign _02_ = _17_;
  (* ram_style = "block" *)
  reg [7:0] \22360  [31:0];
  reg [7:0] _18_;
  always @(posedge clk) begin
    if (rd_en) _18_ <= \22360 [rd_addr];
    if (wr_sel[1]) \22360 [wr_addr] <= wr_data[15:8];
  end
  assign _04_ = _18_;
  (* ram_style = "block" *)
  reg [7:0] \22361  [31:0];
  reg [7:0] _19_;
  always @(posedge clk) begin
    if (rd_en) _19_ <= \22361 [rd_addr];
    if (wr_sel[2]) \22361 [wr_addr] <= wr_data[23:16];
  end
  assign _06_ = _19_;
  (* ram_style = "block" *)
  reg [7:0] \22362  [31:0];
  reg [7:0] _20_;
  always @(posedge clk) begin
    if (rd_en) _20_ <= \22362 [rd_addr];
    if (wr_sel[3]) \22362 [wr_addr] <= wr_data[31:24];
  end
  assign _08_ = _20_;
  (* ram_style = "block" *)
  reg [7:0] \22363  [31:0];
  reg [7:0] _21_;
  always @(posedge clk) begin
    if (rd_en) _21_ <= \22363 [rd_addr];
    if (wr_sel[4]) \22363 [wr_addr] <= wr_data[39:32];
  end
  assign _10_ = _21_;
  (* ram_style = "block" *)
  reg [7:0] \22364  [31:0];
  reg [7:0] _22_;
  always @(posedge clk) begin
    if (rd_en) _22_ <= \22364 [rd_addr];
    if (wr_sel[5]) \22364 [wr_addr] <= wr_data[47:40];
  end
  assign _12_ = _22_;
  (* ram_style = "block" *)
  reg [7:0] \22365  [31:0];
  reg [7:0] _23_;
  always @(posedge clk) begin
    if (rd_en) _23_ <= \22365 [rd_addr];
    if (wr_sel[6]) \22365 [wr_addr] <= wr_data[55:48];
  end
  assign _14_ = _23_;
  (* ram_style = "block" *)
  reg [7:0] \22366  [31:0];
  reg [7:0] _24_;
  always @(posedge clk) begin
    if (rd_en) _24_ <= \22366 [rd_addr];
    if (wr_sel[7]) \22366 [wr_addr] <= wr_data[63:56];
  end
  assign _16_ = _24_;
  always @(posedge clk)
    _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
  assign rd_data = _00_;
endmodule

module plru_1(clk, rst, acc, acc_en, lru);
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  input acc;
  input acc_en;
  input clk;
  output lru;
  input rst;
  reg [1:0] tree;
  assign _0_ = ~ acc;
  assign _1_ = acc_en ? _0_ : tree[1];
  assign _2_ = rst ? 1'h0 : tree[0];
  assign _3_ = rst ? 1'h0 : _1_;
  always @(posedge clk)
    tree <= { _3_, _2_ };
  assign lru = tree[1];
endmodule