From benh@kernel.crashing.org Fri Dec  9 10:42:45 2005
Subject: radeon stuff
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Jeremy Kerr <jk@ozlabs.org>
Content-Type: text/plain
Date: Fri, 09 Dec 2005 10:42:45 +1100

For r200, r300, rv350 and later:

FP_GEN_CNTL &= ~0x00000c07
FP_GEN_CNTL |= 0x00000405 (or 0x00000805 for CRTC1)

For rv200, rv250, rv280:

FP_GEN_CNTL &= ~0x00002007
FP_GEN_CNTL |= 0x00002005 (or 0x00000005 for CRTC1)

(Low bits enable the FP & no blanking, high bit is the routing
to source pixels from CRTC2)

You might also have to set 0x00200000 and/or 0x00030000 depending
on your mileage.

If it doesn't sync try setting 0x00000002 and clearing it (blanking)
or simply try to put the old value back and the new value again.