<html><body>
<p>This looks good to me, thanks for looking over the code.<br>
<br>
Max Aguilar<br>
Linux Kernel/Bootloader/Bring-Up<br>
STI Design Center<br>
(512) 838-5704 T/L 678-5704<br>
maguilar@us.ibm.com<br>
<p><font size="2" color="#800080">To: </font><font size="2">linuxppc64-dev@ozlabs.org</font><br>
<font size="2" color="#800080">cc: </font><font size="2">Milton Miller <miltonm@bga.com>, Paul Mackerras <paulus@samba.org>, Max Aguilar/Austin/IBM@IBMUS</font><font size="2" color="#800080"> </font><br>
<font size="2" color="#800080">Subject: </font><font size="2">[PATCH ] cell: enable pause(0) in cpu_idle</font><br>
<br>
<br>
<tt>This patch enables support for pause(0) power management state<br>
for the Cell Broadband Processor, which is import for power efficient<br>
operation. The pervasive infrastructure will in the future enable<br>
us to introduce more functionality specific to the Cell's<br>
pervasive unit.<br>
<br>
This version contains more changes according to comments from Milton.<br>
More importantly, it now also works on DD2 hardware, after I have<br>
fixed a bug in the initialization sequence.<br>
<br>
From: Maximino Aguilar <maguilar@us.ibm.com><br>
Signed-off-by: Arnd Bergmann <arndb@de.ibm.com><br>
<br>
---<br>
<br>
Paul, please merge this once Milton and Max have both acknowledged<br>
the contents.<br>
<br>
Max, I haven't gotten any reply from you on this patch so far.<br>
Please tell us if the changes I have done to your code look<br>
right!<br>
<br>
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/Makefile<br>
===================================================================<br>
--- linux-2.6.15-rc.orig/arch/powerpc/platforms/cell/Makefile<br>
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/Makefile<br>
@@ -1,4 +1,6 @@<br>
obj-y += interrupt.o iommu.o setup.o spider-pic.o<br>
+obj-y += pervasive.o<br>
+<br>
obj-$(CONFIG_SMP) += smp.o<br>
obj-$(CONFIG_SPU_FS) += spufs/ spu_base.o<br>
builtin-spufs-$(CONFIG_SPU_FS) += spu_syscalls.o<br>
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.c<br>
===================================================================<br>
--- /dev/null<br>
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.c<br>
@@ -0,0 +1,192 @@<br>
+/*<br>
+ * CBE Pervasive Monitor and Debug<br>
+ *<br>
+ * (C) Copyright IBM Corporation 2005<br>
+ *<br>
+ * Authors: Maximino Aguilar (maguilar@us.ibm.com)<br>
+ * Michael N. Day (mnday@us.ibm.com)<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2, or (at your option)<br>
+ * any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.<br>
+ */<br>
+<br>
+#undef DEBUG<br>
+<br>
+#include <linux/config.h><br>
+#include <linux/interrupt.h><br>
+#include <linux/irq.h><br>
+#include <linux/percpu.h><br>
+#include <linux/types.h><br>
+#include <linux/kallsyms.h><br>
+<br>
+#include <asm/io.h><br>
+#include <asm/machdep.h><br>
+#include <asm/prom.h><br>
+#include <asm/pgtable.h><br>
+#include <asm/reg.h><br>
+<br>
+#include "pervasive.h"<br>
+<br>
+struct cbe_pervasive {<br>
+ struct pmd_regs __iomem *regs;<br>
+ unsigned int thread;<br>
+};<br>
+<br>
+/* can't use per_cpu from setup_arch */<br>
+static struct cbe_pervasive cbe_pervasive[NR_CPUS];<br>
+<br>
+static void __init cbe_enable_pause_zero(void)<br>
+{<br>
+ unsigned long thread_switch_control;<br>
+ unsigned long temp_register;<br>
+ struct cbe_pervasive *p;<br>
+ int thread;<br>
+<br>
+ p = &cbe_pervasive[get_cpu()];<br>
+<br>
+ if (!cbe_pervasive->regs)<br>
+ return;<br>
+<br>
+ pr_debug("Power Management: CPU %d\n", smp_processor_id());<br>
+<br>
+ /* Enable Pause(0) control bit */<br>
+ temp_register = in_be64(&p->regs->pm_control);<br>
+<br>
+ out_be64(&p->regs->pm_control,<br>
+ temp_register|PMD_PAUSE_ZERO_CONTROL);<br>
+<br>
+ /* Enable DEC and EE interrupt request */<br>
+ thread_switch_control = mfspr(SPRN_TSC_CELL);<br>
+ thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;<br>
+<br>
+ switch ((mfspr(SPRN_CTRLF) & CTRL_CT)) {<br>
+ case CTRL_CT0:<br>
+ thread_switch_control |= TSC_CELL_DEC_ENABLE_0;<br>
+ thread = 0;<br>
+ break;<br>
+ case CTRL_CT1:<br>
+ thread_switch_control |= TSC_CELL_DEC_ENABLE_1;<br>
+ thread = 1;<br>
+ break;<br>
+ default:<br>
+ printk(KERN_WARNING "%s: unknown configuration\n",<br>
+ __FUNCTION__);<br>
+ thread = -1;<br>
+ break;<br>
+ }<br>
+<br>
+ if (p->thread != thread)<br>
+ printk(KERN_WARNING "%s: device tree inconsistant, "<br>
+ "cpu %i: %d/%d\n", __FUNCTION__,<br>
+ smp_processor_id(),<br>
+ p->thread, thread);<br>
+<br>
+ mtspr(SPRN_TSC_CELL, thread_switch_control);<br>
+<br>
+ put_cpu();<br>
+}<br>
+<br>
+static void cbe_idle(void)<br>
+{<br>
+ unsigned long ctrl;<br>
+<br>
+ cbe_enable_pause_zero();<br>
+<br>
+ while (1) {<br>
+ if (!need_resched()) {<br>
+ while (!need_resched()) {<br>
+ /* go into low thread priority */<br>
+ HMT_low();<br>
+<br>
+ /* go into low power mode */<br>
+ local_irq_disable();<br>
+ ctrl = mfspr(SPRN_CTRLF);<br>
+ ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);<br>
+ mtspr(SPRN_CTRLT, ctrl);<br>
+ local_irq_enable();<br>
+ }<br>
+ /* restore thread prio */<br>
+ HMT_medium();<br>
+ }<br>
+<br>
+ ppc64_runlatch_on();<br>
+ preempt_enable_no_resched();<br>
+ schedule();<br>
+ preempt_disable();<br>
+ }<br>
+}<br>
+<br>
+static int __init cbe_find_pmd_mmio(int cpu, struct cbe_pervasive *p)<br>
+{<br>
+ struct device_node *node;<br>
+ unsigned int *int_servers;<br>
+ char *addr;<br>
+ unsigned long real_address;<br>
+ unsigned int size;<br>
+<br>
+ struct pmd_regs __iomem *pmd_mmio_area;<br>
+ int hardid, thread;<br>
+ int proplen;<br>
+<br>
+ pmd_mmio_area = NULL;<br>
+ hardid = get_hard_smp_processor_id(cpu);<br>
+ for (node = NULL; (node = of_find_node_by_type(node, "cpu"));) {<br>
+ int_servers = (void *) get_property(node,<br>
+ "ibm,ppc-interrupt-server#s", &proplen);<br>
+ if (!int_servers) {<br>
+ printk(KERN_WARNING "CPU device misses "<br>
+ "ibm,ppc-interrupt-server#s property");<br>
+ continue;<br>
+ }<br>
+ for (thread = 0; thread < proplen / sizeof (int); thread++) {<br>
+ if (hardid == int_servers[thread]) {<br>
+ addr = get_property(node, "pervasive", NULL);<br>
+ goto found;<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ printk(KERN_WARNING "%s: CPU %d not found\n", __FUNCTION__, cpu);<br>
+ return -EINVAL;<br>
+<br>
+found:<br>
+ real_address = *(unsigned long*) addr;<br>
+ addr += sizeof (unsigned long);<br>
+ size = *(unsigned int*) addr;<br>
+<br>
+ pr_debug("pervasive area for CPU %d at %lx, size %x\n",<br>
+ cpu, real_address, size);<br>
+ p->regs = __ioremap(real_address, size, _PAGE_NO_CACHE);<br>
+ p->thread = thread;<br>
+ return 0;<br>
+}<br>
+<br>
+void __init cell_pervasive_init(void)<br>
+{<br>
+ struct cbe_pervasive *p;<br>
+ int cpu;<br>
+ int ret;<br>
+<br>
+ if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))<br>
+ return;<br>
+<br>
+ for_each_cpu(cpu) {<br>
+ p = &cbe_pervasive[cpu];<br>
+ ret = cbe_find_pmd_mmio(cpu, p);<br>
+ if (ret)<br>
+ return;<br>
+ }<br>
+<br>
+ ppc_md.idle_loop = cbe_idle;<br>
+}<br>
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.h<br>
===================================================================<br>
--- /dev/null<br>
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.h<br>
@@ -0,0 +1,62 @@<br>
+/*<br>
+ * Cell Pervasive Monitor and Debug interface and HW structures<br>
+ *<br>
+ * (C) Copyright IBM Corporation 2005<br>
+ *<br>
+ * Authors: Maximino Aguilar (maguilar@us.ibm.com)<br>
+ * David J. Erb (djerb@us.ibm.com)<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2, or (at your option)<br>
+ * any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.<br>
+ */<br>
+<br>
+<br>
+#ifndef PERVASIVE_H<br>
+#define PERVASIVE_H<br>
+<br>
+struct pmd_regs {<br>
+ u8 pad_0x0000_0x0800[0x0800 - 0x0000]; /* 0x0000 */<br>
+<br>
+ /* Thermal Sensor Registers */<br>
+ u64 ts_ctsr1; /* 0x0800 */<br>
+ u64 ts_ctsr2; /* 0x0808 */<br>
+ u64 ts_mtsr1; /* 0x0810 */<br>
+ u64 ts_mtsr2; /* 0x0818 */<br>
+ u64 ts_itr1; /* 0x0820 */<br>
+ u64 ts_itr2; /* 0x0828 */<br>
+ u64 ts_gitr; /* 0x0830 */<br>
+ u64 ts_isr; /* 0x0838 */<br>
+ u64 ts_imr; /* 0x0840 */<br>
+ u64 tm_cr1; /* 0x0848 */<br>
+ u64 tm_cr2; /* 0x0850 */<br>
+ u64 tm_simr; /* 0x0858 */<br>
+ u64 tm_tpr; /* 0x0860 */<br>
+ u64 tm_str1; /* 0x0868 */<br>
+ u64 tm_str2; /* 0x0870 */<br>
+ u64 tm_tsr; /* 0x0878 */<br>
+<br>
+ /* Power Management */<br>
+ u64 pm_control; /* 0x0880 */<br>
+#define PMD_PAUSE_ZERO_CONTROL 0x10000<br>
+ u64 pm_status; /* 0x0888 */<br>
+<br>
+ /* Time Base Register */<br>
+ u64 tbr; /* 0x0890 */<br>
+<br>
+ u8 pad_0x0898_0x1000 [0x1000 - 0x0898]; /* 0x0898 */<br>
+};<br>
+<br>
+void __init cell_pervasive_init(void);<br>
+<br>
+#endif<br>
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/setup.c<br>
===================================================================<br>
--- linux-2.6.15-rc.orig/arch/powerpc/platforms/cell/setup.c<br>
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/setup.c<br>
@@ -49,6 +49,7 @@<br>
<br>
#include "interrupt.h"<br>
#include "iommu.h"<br>
+#include "pervasive.h"<br>
<br>
#ifdef DEBUG<br>
#define DBG(fmt...) udbg_printf(fmt)<br>
@@ -165,6 +166,7 @@ static void __init cell_setup_arch(void)<br>
init_pci_config_tokens();<br>
find_and_init_phbs();<br>
spider_init_IRQ();<br>
+ cell_pervasive_init();<br>
#ifdef CONFIG_DUMMY_CONSOLE<br>
conswitchp = &dummy_con;<br>
#endif<br>
Index: linux-2.6.15-rc/arch/powerpc/kernel/head_64.S<br>
===================================================================<br>
--- linux-2.6.15-rc.orig/arch/powerpc/kernel/head_64.S<br>
+++ linux-2.6.15-rc/arch/powerpc/kernel/head_64.S<br>
@@ -401,7 +401,7 @@ label##_common: \<br>
.globl __start_interrupts<br>
__start_interrupts:<br>
<br>
- STD_EXCEPTION_PSERIES(0x100, system_reset)<br>
+ STD_EXCEPTION_PSERIES(0x100, system_reset_check)<br>
<br>
. = 0x200<br>
_machine_check_pSeries:<br>
@@ -880,6 +880,28 @@ unrecov_fer:<br>
bl .unrecoverable_exception<br>
b 1b<br>
<br>
+/* This is a new system reset handler for the BE processor.<br>
+ * SRR1 stores wake information that must be decoded to determine why<br>
+ * the processor was at the system reset handler.<br>
+ */<br>
+<br>
+ .align 7<br>
+ .globl system_reset_check_common<br>
+system_reset_check_common:<br>
+BEGIN_FTR_SECTION<br>
+ mr r22,r12 /* r12 has SRR1 saved */<br>
+ srwi r22,r22,16<br>
+ andi. r22,r22,MSR_WAKEMASK<br>
+ cmpwi r22,MSR_WAKEEE<br>
+ beq hardware_interrupt_common<br>
+ cmpwi r22,MSR_WAKEDEC<br>
+ beq decrementer_common<br>
+ cmpwi r22,MSR_WAKEMT<br>
+ bne system_reset_common<br>
+END_FTR_SECTION_IFSET(CPU_FTR_PAUSE_ZERO)<br>
+ EXCEPTION_PROLOG_COMMON(0x100, PACA_EXGEN);<br>
+ b fast_exception_return<br>
+<br>
/*<br>
* Here r13 points to the paca, r9 contains the saved CR,<br>
* SRR0 and SRR1 are saved in r11 and r12,<br>
Index: linux-2.6.15-rc/include/asm-powerpc/cputable.h<br>
===================================================================<br>
--- linux-2.6.15-rc.orig/include/asm-powerpc/cputable.h<br>
+++ linux-2.6.15-rc/include/asm-powerpc/cputable.h<br>
@@ -106,6 +106,7 @@ extern void do_cpu_ftr_fixups(unsigned l<br>
#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)<br>
#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)<br>
#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)<br>
+#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)<br>
#else<br>
/* ensure on 32b processors the flags are available for compiling but<br>
* don't do anything */<br>
@@ -305,7 +306,8 @@ enum {<br>
CPU_FTR_MMCRA_SIHV,<br>
CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |<br>
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |<br>
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,<br>
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |<br>
+ CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,<br>
CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |<br>
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,<br>
#endif<br>
Index: linux-2.6.15-rc/include/asm-powerpc/reg.h<br>
===================================================================<br>
--- linux-2.6.15-rc.orig/include/asm-powerpc/reg.h<br>
+++ linux-2.6.15-rc/include/asm-powerpc/reg.h<br>
@@ -92,6 +92,15 @@<br>
#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */<br>
#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */<br>
<br>
+/* Wake Events */<br>
+#define MSR_WAKEMASK 0x0038<br>
+#define MSR_WAKERESET 0x0038<br>
+#define MSR_WAKESYSERR 0x0030<br>
+#define MSR_WAKEEE 0x0020<br>
+#define MSR_WAKEMT 0x0028<br>
+#define MSR_WAKEDEC 0x0018<br>
+#define MSR_WAKETHERM 0x0010<br>
+<br>
#ifdef CONFIG_PPC64<br>
#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF<br>
#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV<br>
@@ -145,6 +154,10 @@<br>
#define SPRN_CTR 0x009 /* Count Register */<br>
#define SPRN_CTRLF 0x088<br>
#define SPRN_CTRLT 0x098<br>
+#define CTRL_CT 0xc0000000 /* current thread */<br>
+#define CTRL_CT0 0x80000000 /* thread 0 */<br>
+#define CTRL_CT1 0x40000000 /* thread 1 */<br>
+#define CTRL_TE 0x00c00000 /* thread enable */<br>
#define CTRL_RUNLATCH 0x1<br>
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */<br>
#define DABR_TRANSLATION (1UL << 2)<br>
@@ -257,11 +270,11 @@<br>
#define SPRN_HID6 0x3F9 /* BE HID 6 */<br>
#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */<br>
#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */<br>
-#define SPRN_TSCR 0x399 /* Thread switch control on BE */<br>
-#define SPRN_TTR 0x39A /* Thread switch timeout on BE */<br>
-#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */<br>
-#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */<br>
-#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */<br>
+#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */<br>
+#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */<br>
+#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */<br>
+#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */<br>
+#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */<br>
#define SPRN_TSC 0x3FD /* Thread switch control on others */<br>
#define SPRN_TST 0x3FC /* Thread switch timeout on others */<br>
#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)<br>
Index: linux-2.6.15-rc/arch/powerpc/kernel/cputable.c<br>
===================================================================<br>
--- linux-2.6.15-rc.orig/arch/powerpc/kernel/cputable.c<br>
+++ linux-2.6.15-rc/arch/powerpc/kernel/cputable.c<br>
@@ -273,7 +273,7 @@ struct cpu_spec cpu_specs[] = {<br>
.oprofile_model = &op_model_power4,<br>
#endif<br>
},<br>
- { /* BE DD1.x */<br>
+ { /* Cell Broadband Engine */<br>
.pvr_mask = 0xffff0000,<br>
.pvr_value = 0x00700000,<br>
.cpu_name = "Cell Broadband Engine",<br>
</tt><br>
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