<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META NAME="Generator" CONTENT="MS Exchange Server version 6.5.7652.24">
<TITLE>RE: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedata cache)</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/plain format -->
<BR>
<P><FONT SIZE=2>arch/powerpc/boot/virtex405-head.S has:<BR>
<BR>
#include "ppc_asm.h"<BR>
<BR>
.text<BR>
.global _zimage_start<BR>
_zimage_start:<BR>
<BR>
/* PPC errata 213: needed by Virtex-4 FX */<BR>
mfccr0 0<BR>
oris 0,0,0x50000000@h<BR>
mtccr0 0<BR>
<BR>
So, this happens first before anything else.<BR>
Without this, the boards that I've used crash pretty quickly, so it may be obvious that the status register is set properly.<BR>
As a result, you probably need to do it in the boot loader and not in the kernel proper.<BR>
<BR>
Steve<BR>
<BR>
-----Original Message-----<BR>
From: linuxppc-embedded-bounces+stephen=neuendorffer.name@ozlabs.org on behalf of Darcy Watkins<BR>
Sent: Tue 8/26/2008 9:01 AM<BR>
To: linuxppc-embedded<BR>
Subject: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedata cache)<BR>
<BR>
Hello,<BR>
<BR>
The IBM/AMCC errata document recommends setting reserved bits 1 & 3 in<BR>
CCR0 as a workaround to PPC405EP errata CPU 213 (Incorrect data may be<BR>
flushed from the data cache). For a start, I just tried hacking in a<BR>
few lines of assembly code into...<BR>
<BR>
arch/powerpc/kernel/head_40x.S<BR>
<BR>
---<BR>
<BR>
Around line #839 ...<BR>
<BR>
bl early_init /* We have to do this with MMU on */<BR>
<BR>
/*<BR>
* Decide what sort of machine this is and initialize the MMU.<BR>
*/<BR>
mr r3,r31<BR>
mr r4,r30<BR>
mr r5,r29<BR>
mr r6,r28<BR>
mr r7,r27<BR>
bl machine_init<BR>
bl MMU_init<BR>
/* DLW hack!! - for PPC405EP errata CPU 213 */<BR>
mfspr r4,SPRN_CCR0<BR>
oris r4,r4,0x5000<BR>
mtspr SPRN_CCR0,r4<BR>
isync<BR>
<BR>
/* Go back to running unmapped so we can load up new values<BR>
* and change to using our exception vectors.<BR>
* On the 4xx, all we have to do is invalidate the TLB to clear<BR>
* the old 16M byte TLB mappings.<BR>
*/<BR>
lis r4,2f@h<BR>
...<BR>
<BR>
Since I am not a PowerPC assembler guru, does this appear right?<BR>
<BR>
I think that eventually I'd want to create a cpu_setup_40x.S with the<BR>
fixup code as part of a setup_cpu_405ep function and then hook this into<BR>
cputable.c, but first I want to make sure that the errata workaround is<BR>
actually taking effect (and also not being undone by later startup<BR>
code).<BR>
<BR>
--<BR>
<BR>
<BR>
Regards,<BR>
<BR>
Darcy<BR>
<BR>
--------------<BR>
Darcy L. Watkins - Senior Software Developer<BR>
Tranzeo Wireless Technologies, Inc.<BR>
19273 Fraser Way, Pitt Meadows, BC, Canada V3Y 2V4<BR>
T:604-460-6002 ext:410<BR>
<A HREF="http://www.tranzeo.com">http://www.tranzeo.com</A><BR>
<BR>
<BR>
_______________________________________________<BR>
Linuxppc-embedded mailing list<BR>
Linuxppc-embedded@ozlabs.org<BR>
<A HREF="https://ozlabs.org/mailman/listinfo/linuxppc-embedded">https://ozlabs.org/mailman/listinfo/linuxppc-embedded</A><BR>
<BR>
<BR>
</FONT>
</P>
<br clear=all> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
</BODY>
</HTML>