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Dear Johann,<BR>
Thanks for the prompt reply. <BR>
<BR>
Actually I am using EDK 10.1 evaluation version. According to Xilinx's answer, they said the problem will be fixed in 10.1 already. Unfortunately I still met it in my design. <BR>
<BR>
Do you happen to still have the file tx_ii_if.zip? I cannot download it from Xilinx any more. Thank you so much if you can give me a copy.<BR>
<BR>
BR<BR>
Ming<BR>
<BR>
<BR>> Date: Fri, 4 Apr 2008 09:53:07 +0000<BR>> From: johaahn@gmail.com<BR>> To: eemingliu@hotmail.com<BR>> Subject: Re: Xilinx LLTEMAC driver issues<BR>> CC: mh@omnisys.se; linuxppc-embedded@ozlabs.org; john.linn@xilinx.com; git@xilinx.com<BR>> <BR>> Hi Ming,<BR>> <BR>> I've already used netperf (without NFS) successfully.<BR>> Are you using 1.00.b and 9.2, if yes look at AR #29708.<BR>> <BR>> Best regards,<BR>> Johann<BR>> <BR>> On Fri, Apr 4, 2008 at 9:36 AM, MingLiu <eemingliu@hotmail.com> wrote:<BR>> ><BR>> > Dear Johann,<BR>> > Previously I said this patch helps for the checksum error problem. But now<BR>> > I found some new issues. Yes. at least with this patch, something is better<BR>> > and at least we can use the hardware checksum offloading to do something,<BR>> > for example I can mount the NFS root file system. However when I try to<BR>> > measure the ethernet bandwidth with netperf, something goes wrong and the<BR>> > NFS mount will be broken. I guess this is because of the large bulk data<BR>> > transfer and maybe thus it triggers the checksum problem to happen.<BR>> ><BR>> > Do you have the same situation? Or someone else has the same problem? I<BR>> > will appreciate if you can share your experience. Thanks a lot.<BR>> ><BR>> > BR<BR>> > Ming<BR>> ><BR>> ><BR>> ><BR>> > ________________________________<BR>> > Date: Wed, 2 Apr 2008 07:20:43 +0000<BR>> > From: johaahn@gmail.com<BR>> > To: mh@omnisys.se<BR>> ><BR>> > Subject: Re: Xilinx LLTEMAC driver issues<BR>> > CC: linuxppc-embedded@ozlabs.org; John.Linn@xilinx.com; git@xilinx.com<BR>> ><BR>> ><BR>> ><BR>> > I've solved this checksum offloading issue with this below patch.<BR>> > It may help, if you need performance. It certainly needs review but it works<BR>> > on my side.<BR>> ><BR>> > --- xilinxgit/drivers/net/xilinx<BR>> > _lltemac/xlltemac_main.c.orig 2008-03-21 09:11:43.000000000 +0100<BR>> > +++ xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c 2008-03-21<BR>> > 09:24:23.000000000 +0100<BR>> > @@ -133,7 +133,7 @@<BR>> > (XLlDma_mBdRead((BdPtr), XLLDMA_BD_STSCTRL_USR0_OFFSET)) &<BR>> > 0xFFFFFFFE )<BR>> ><BR>> > #define BdCsumSetup(BdPtr, Start, Insert) \<BR>> > - XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 |<BR>> > (Insert))<BR>> > + XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) |<BR>> > (Insert))<BR>> ><BR>> > /* Used for debugging */<BR>> > #define BdCsumInsert(BdPtr) \<BR>> > @@ -1540,7 +1541,7 @@ static int xenet_DmaSend_internal(struct<BR>> > /*<BR>> > * if tx checksum offloading is enabled, when the ethernet stack<BR>> > * wants us to perform the checksum in hardware,<BR>> > - * skb->ip_summed is CHECKSUM_COMPLETE. Otherwise skb->ip_summed is<BR>> > + * skb->ip_summed is CHECKSUM_PARTIAL. Otherwise skb->ip_summed is<BR>> > * CHECKSUM_NONE, meaning the checksum is already done, or<BR>> > * CHECKSUM_UNNECESSARY, meaning checksumming is turned off (e.g.<BR>> > * loopback interface)<BR>> > @@ -1565,9 +1566,11 @@ static int xenet_DmaSend_internal(struct<BR>> > * skb_transport_header(skb) points to the beginning of the ip header<BR>> > *<BR>> > */<BR>> > - if (skb->ip_summed == CHECKSUM_COMPLETE) {<BR>> > + if (skb->ip_summed == CHECKSUM_PARTIAL) {<BR>> > +<BR>> > + unsigned int csum_start_off = skb_transport_offset(skb);<BR>> > + unsigned int csum_index_off = csum_start_off + skb->csum_offset;<BR>> ><BR>> > - unsigned char *raw = skb_transport_header(skb);<BR>> > #if 0<BR>> > {<BR>> > unsigned int csum = _xenet_tx_csum(skb);<BR>> > @@ -1578,9 +1581,8 @@ static int xenet_DmaSend_internal(struct<BR>> > }<BR>> > #else<BR>> > BdCsumEnable(bd_ptr);<BR>> > - BdCsumSetup(bd_ptr, raw - skb->data,<BR>> > - (raw - skb->data) + skb->csum);<BR>> > -<BR>> > + BdCsumSetup(bd_ptr, csum_start_off,<BR>> > + csum_index_off);<BR>> > #endif<BR>> > lp->tx_hw_csums++;<BR>> > }<BR>> > @@ -3277,7 +3279,7 @@ static int __devinit xtenet_of_probe(str<BR>> > struct resource *r_irq = &r_irq_struct; /* Interrupt resources */<BR>> > struct resource *r_mem = &r_mem_struct; /* IO mem resources */<BR>> > struct xlltemac_platform_data *pdata = &pdata_struct;<BR>> > - void *mac_address;<BR>> > + const void *mac_address;<BR>> > int rc = 0;<BR>> > const phandle *llink_connected_handle;<BR>> > struct device_node *llink_connected_node;<BR>> ><BR>> ><BR>> > On Mon, Mar 31, 2008 at 11:10 AM, Magnus Hjorth <mh@omnisys.se> wrote:<BR>> ><BR>> > Deactivating checksum offloading helped a lot! I still have some packet loss<BR>> > and not the best performance (TFTP transfer about 100 kbyte/s) but at least<BR>> > it works.<BR>> ><BR>> > Thanks!<BR>> ><BR>> > //Magnus<BR>> ><BR>> ><BR>> ><BR>> ><BR>> > > -----Original Message-----<BR>> > > From: rza1 [mailto:rza1@so-logic.net]<BR>> > > Sent: den 31 mars 2008 11:14<BR>> > > To: Magnus Hjorth<BR>> > > Cc: John Linn; git; linuxppc-embedded@ozlabs.org<BR>> > > Subject: Re: Xilinx LLTEMAC driver issues<BR>> > ><BR>> > > Hi Magnus,<BR>> > ><BR>> > > 1.<BR>> > > I am using nearly the same versions then you and got the same problems<BR>> > > too ;-).<BR>> > > I think there are some problems with the checksum offloading.<BR>> > > Try to sniff the some packages (e.g. wireshark)...<BR>> > > For me ICMP (ping) worked but udp and tcp not (because off a wrong<BR>> > > checksum in the transport layer).<BR>> > > A quick solution is to just deactivate checksum offloading.<BR>> > ><BR>> > > 2.<BR>> > > I remember some problems with Virtex-4 presamples too.<BR>> > > There where problems with the hard-temac wrapper. You had to use 1.00.a<BR>> > > and not b version.<BR>> > > But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.<BR>> > ><BR>> > > all the best,<BR>> > > Robert<BR>> > ><BR>> > > Magnus Hjorth wrote:<BR>> > > > Hi John,<BR>> > > ><BR>> > > > Thanks for the very fast reply! Right now I'm not at work so I don't<BR>> > > > have the board or EDK here to test anything.<BR>> > > ><BR>> > > > I'm using checksum offload, but I don't know if DRE is enabled or not. I<BR>> > > > can't recall seeing any setting to enable/disable DRE..<BR>> > > ><BR>> > > > A few things that crossed my mind:<BR>> > > ><BR>> > > > Last year I did a design with EDK 8.2, back then there was an issue with<BR>> > > > the ML403 boards having an old revision of the FPGA which wasn't<BR>> > > > compatible with some versions of the IP core. There are no such version<BR>> > > > issues with the xps_ll_temac?<BR>> > > ><BR>> > > > I don't think that I had phy-addr set in the DTS file. Will test that on<BR>> > > > Monday.<BR>> > > ><BR>> > > > Best regards,<BR>> > > > Magnus<BR>> > > ><BR>> > > ><BR>> > > > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:<BR>> > > ><BR>> > > >> Hi Magnus,<BR>> > > >><BR>> > > >> Sorry to hear you're having problems with it.<BR>> > > >><BR>> > > >> I am doing testing on an ML405 which is the same board but with a<BR>> > bigger<BR>> > > FPGA, but with ppc arch and I don't see this issue. I have done limited<BR>> > testing<BR>> > > with powerpc arch and the LL TEMAC, but I didn't see this issue there<BR>> > either.<BR>> > > Powerpc arch is definitely less mature in my experience than the ppc arch.<BR>> > I'll<BR>> > > do a quick test with my powerpc arch and make sure again I'm not seeing<BR>> > it.<BR>> > > >><BR>> > > >> My kernel is from the Xilinx Git tree, but there have been a number of<BR>> > > changes we have pushed out so I don't know how long ago you pulled from<BR>> > the Git<BR>> > > tree.<BR>> > > >><BR>> > > >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC<BR>> > 1.01a so<BR>> > > it's a little newer. I reviewed the change log for the LL TEMAC and don't<BR>> > see<BR>> > > any big problems that were fixed in the newer versions, more new features.<BR>> > I'll<BR>> > > check with some others here to see if I missed something there.<BR>> > > >><BR>> > > >> I am using DMA also, but no DRE or checksum offload. You didn't say<BR>> > anything<BR>> > > about those. I'm going to insert my mhs file that describes my system to<BR>> > let you<BR>> > > compare your system configuration. It's not clear to me yet if you have a<BR>> > h/w or<BR>> > > s/w problem.<BR>> > > >><BR>> > > >> I'll also insert some of my device tree with the LL TEMAC so you can<BR>> > compare<BR>> > > (ignore 16550 stuff as we are still working on that).<BR>> > > >><BR>> > > >> Since you can't ping reliably I would probably focus on that since it's<BR>> > > simpler than the other issues you're seeing.<BR>> > > >><BR>> > > >> Thanks,<BR>> > > >> John<BR>> > > >><BR>> > > >><BR>> > > >><BR>> > > >> #<BR>> > ><BR>> > ##############################################################################<BR>> > > >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build<BR>> > > EDK_K_SP1.1<BR>> > > >> # Thu Feb 14 14:11:12 2008<BR>> > > >> # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1<BR>> > > >> # Family: virtex4<BR>> > > >> # Device: xc4vfx20<BR>> > > >> # Package: ff672<BR>> > > >> # Speed Grade: -10<BR>> > > >> # Processor: ppc405_0<BR>> > > >> # Processor clock frequency: 300.00 MHz<BR>> > > >> # Bus clock frequency: 100.00 MHz<BR>> > > >> # On Chip Memory : 8 KB<BR>> > > >> # Total Off Chip Memory : 128 MB<BR>> > > >> # - DDR_SDRAM = 128 MB<BR>> > > >> #<BR>> > ><BR>> > ##############################################################################<BR>> > > >> PARAMETER VERSION = 2.1.0<BR>> > > >><BR>> > > >><BR>> > > >> PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I<BR>> > > >> PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O<BR>> > > >> PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR =<BR>> > IO, VEC<BR>> > > = [0:3]<BR>> > > >> PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO<BR>> > > >> PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O<BR>> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =<BR>> > > fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR<BR>> > = O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR =<BR>> > O, VEC<BR>> > > = [12:0]<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =<BR>> > fpga_0_DDR_SDRAM_DDR_BankAddr, DIR<BR>> > > = O, VEC = [1:0]<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR<BR>> > = O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR =<BR>> > O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR<BR>> > = O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR =<BR>> > O<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O,<BR>> > VEC =<BR>> > > [3:0]<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO,<BR>> > VEC =<BR>> > > [3:0]<BR>> > > >> PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC<BR>> > =<BR>> > > [31:0]<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =<BR>> > fpga_0_TriMode_MAC_GMII_MDIO_0,<BR>> > > DIR = IO<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =<BR>> > fpga_0_TriMode_MAC_GMII_MDC_0, DIR<BR>> > > = O<BR>> > > >> PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =<BR>> > > fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O<BR>> > > >> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =<BR>> > 100000000<BR>> > > >> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST<BR>> > > >><BR>> > > >><BR>> > > >> BEGIN ppc405_virtex4<BR>> > > >> PARAMETER INSTANCE = ppc405_0<BR>> > > >> PARAMETER HW_VER = 2.01.a<BR>> > > >> PARAMETER C_FASTEST_PLB_CLOCK = DPLB1<BR>> > > >> PARAMETER C_IDCR_BASEADDR = 0b0100000000<BR>> > > >> PARAMETER C_IDCR_HIGHADDR = 0b0111111111<BR>> > > >> BUS_INTERFACE JTAGPPC = jtagppc_0_0<BR>> > > >> BUS_INTERFACE IPLB0 = plb<BR>> > > >> BUS_INTERFACE DPLB0 = plb<BR>> > > >> BUS_INTERFACE IPLB1 = ppc405_0_iplb1<BR>> > > >> BUS_INTERFACE DPLB1 = ppc405_0_dplb1<BR>> > > >> BUS_INTERFACE RESETPPC = ppc_reset_bus<BR>> > > >> PORT CPMC405CLOCK = proc_clk_s<BR>> > > >> PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN jtagppc_cntlr<BR>> > > >> PARAMETER INSTANCE = jtagppc_0<BR>> > > >> PARAMETER HW_VER = 2.01.a<BR>> > > >> BUS_INTERFACE JTAGPPC0 = jtagppc_0_0<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN plb_v46<BR>> > > >> PARAMETER INSTANCE = plb<BR>> > > >> PARAMETER C_DCR_INTFCE = 0<BR>> > > >> PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100<BR>> > > >> PARAMETER HW_VER = 1.02.a<BR>> > > >> PORT PLB_Clk = sys_clk_s<BR>> > > >> PORT SYS_Rst = sys_bus_reset<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_bram_if_cntlr<BR>> > > >> PARAMETER INSTANCE = xps_bram_if_cntlr_1<BR>> > > >> PARAMETER HW_VER = 1.00.a<BR>> > > >> PARAMETER C_SPLB_NATIVE_DWIDTH = 64<BR>> > > >> PARAMETER C_BASEADDR = 0xffffe000<BR>> > > >> PARAMETER C_HIGHADDR = 0xffffffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN bram_block<BR>> > > >> PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram<BR>> > > >> PARAMETER HW_VER = 1.00.a<BR>> > > >> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_uart16550<BR>> > > >> PARAMETER INSTANCE = RS232_Uart<BR>> > > >> PARAMETER HW_VER = 2.00.a<BR>> > > >> PARAMETER C_IS_A_16550 = 1<BR>> > > >> PARAMETER C_BASEADDR = 0x83e00000<BR>> > > >> PARAMETER C_HIGHADDR = 0x83e0ffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> PORT sin = fpga_0_RS232_Uart_sin<BR>> > > >> PORT sout = fpga_0_RS232_Uart_sout<BR>> > > >> PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_gpio<BR>> > > >> PARAMETER INSTANCE = LEDs_4Bit<BR>> > > >> PARAMETER HW_VER = 1.00.a<BR>> > > >> PARAMETER C_INTERRUPT_PRESENT = 1<BR>> > > >> PARAMETER C_GPIO_WIDTH = 4<BR>> > > >> PARAMETER C_IS_DUAL = 0<BR>> > > >> PARAMETER C_IS_BIDIR = 1<BR>> > > >> PARAMETER C_ALL_INPUTS = 0<BR>> > > >> PARAMETER C_BASEADDR = 0x81400000<BR>> > > >> PARAMETER C_HIGHADDR = 0x8140ffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO<BR>> > > >> PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_iic<BR>> > > >> PARAMETER INSTANCE = IIC_EEPROM<BR>> > > >> PARAMETER HW_VER = 2.00.a<BR>> > > >> PARAMETER C_CLK_FREQ = 100000000<BR>> > > >> PARAMETER C_IIC_FREQ = 100000<BR>> > > >> PARAMETER C_TEN_BIT_ADR = 0<BR>> > > >> PARAMETER C_BASEADDR = 0x81600000<BR>> > > >> PARAMETER C_HIGHADDR = 0x8160ffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> PORT Scl = fpga_0_IIC_EEPROM_Scl<BR>> > > >> PORT Sda = fpga_0_IIC_EEPROM_Sda<BR>> > > >> PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_sysace<BR>> > > >> PARAMETER INSTANCE = SysACE_CompactFlash<BR>> > > >> PARAMETER HW_VER = 1.00.a<BR>> > > >> PARAMETER C_MEM_WIDTH = 16<BR>> > > >> PARAMETER C_BASEADDR = 0x83600000<BR>> > > >> PARAMETER C_HIGHADDR = 0x8360ffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK<BR>> > > >> PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split<BR>> > > >> PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD<BR>> > > >> PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN<BR>> > > >> PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN<BR>> > > >> PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN<BR>> > > >> PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ<BR>> > > >> PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN mpmc<BR>> > > >> PARAMETER INSTANCE = DDR_SDRAM<BR>> > > >> PARAMETER HW_VER = 4.00.a<BR>> > > >> PARAMETER C_NUM_PORTS = 3<BR>> > > >> PARAMETER C_MEM_PARTNO = HYB25D512160BE-5<BR>> > > >> PARAMETER C_MEM_DATA_WIDTH = 32<BR>> > > >> PARAMETER C_MEM_DQS_WIDTH = 4<BR>> > > >> PARAMETER C_MEM_DM_WIDTH = 4<BR>> > > >> PARAMETER C_MEM_TYPE = DDR<BR>> > > >> PARAMETER C_NUM_IDELAYCTRL = 2<BR>> > > >> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2<BR>> > > >> PARAMETER C_PIM0_BASETYPE = 2<BR>> > > >> PARAMETER C_PIM1_BASETYPE = 2<BR>> > > >> PARAMETER C_PIM2_BASETYPE = 3<BR>> > > >> PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000<BR>> > > >> PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1<BR>> > > >> PARAMETER C_MPMC_BASEADDR = 0x00000000<BR>> > > >> PARAMETER C_MPMC_HIGHADDR = 0x07ffffff<BR>> > > >> PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000<BR>> > > >> PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff<BR>> > > >> BUS_INTERFACE SPLB0 = ppc405_0_iplb1<BR>> > > >> BUS_INTERFACE SPLB1 = ppc405_0_dplb1<BR>> > > >> BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0<BR>> > > >> BUS_INTERFACE SDMA_CTRL2 = plb<BR>> > > >> PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr<BR>> > > >> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr<BR>> > > >> PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n<BR>> > > >> PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE<BR>> > > >> PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n<BR>> > > >> PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n<BR>> > > >> PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n<BR>> > > >> PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM<BR>> > > >> PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS<BR>> > > >> PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ<BR>> > > >> PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk<BR>> > > >> PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n<BR>> > > >> PORT MPMC_Clk0 = sys_clk_s<BR>> > > >> PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s<BR>> > > >> PORT SDMA2_Clk = sys_clk_s<BR>> > > >> PORT MPMC_Clk_200MHz = clk_200mhz_s<BR>> > > >> PORT MPMC_Rst = sys_periph_reset<BR>> > > >> PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut<BR>> > > >> PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_ll_temac<BR>> > > >> PARAMETER INSTANCE = TriMode_MAC_GMII<BR>> > > >> PARAMETER HW_VER = 1.01.a<BR>> > > >> PARAMETER C_SPLB_CLK_PERIOD_PS = 10000<BR>> > > >> PARAMETER C_PHY_TYPE = 1<BR>> > > >> PARAMETER C_NUM_IDELAYCTRL = 4<BR>> > > >> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-<BR>> > > IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3<BR>> > > >> PARAMETER C_TEMAC_TYPE = 1<BR>> > > >> PARAMETER C_BUS2CORE_CLK_RATIO = 1<BR>> > > >> PARAMETER C_BASEADDR = 0x81c00000<BR>> > > >> PARAMETER C_HIGHADDR = 0x81c0ffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0<BR>> > > >> PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0<BR>> > > >> PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0<BR>> > > >> PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0<BR>> > > >> PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0<BR>> > > >> PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0<BR>> > > >> PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0<BR>> > > >> PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0<BR>> > > >> PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0<BR>> > > >> PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0<BR>> > > >> PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0<BR>> > > >> PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0<BR>> > > >> PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n<BR>> > > >> PORT GTX_CLK_0 = temac_clk_s<BR>> > > >> PORT REFCLK = clk_200mhz_s<BR>> > > >> PORT LlinkTemac0_CLK = sys_clk_s<BR>> > > >> PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN util_bus_split<BR>> > > >> PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0<BR>> > > >> PARAMETER HW_VER = 1.00.a<BR>> > > >> PARAMETER C_SIZE_IN = 7<BR>> > > >> PARAMETER C_LEFT_POS = 0<BR>> > > >> PARAMETER C_SPLIT = 6<BR>> > > >> PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split<BR>> > > >> PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN plb_v46<BR>> > > >> PARAMETER INSTANCE = ppc405_0_iplb1<BR>> > > >> PARAMETER HW_VER = 1.02.a<BR>> > > >> PORT PLB_Clk = sys_clk_s<BR>> > > >> PORT SYS_Rst = sys_bus_reset<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN plb_v46<BR>> > > >> PARAMETER INSTANCE = ppc405_0_dplb1<BR>> > > >> PARAMETER HW_VER = 1.02.a<BR>> > > >> PORT PLB_Clk = sys_clk_s<BR>> > > >> PORT SYS_Rst = sys_bus_reset<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN clock_generator<BR>> > > >> PARAMETER INSTANCE = clock_generator_0<BR>> > > >> PARAMETER HW_VER = 2.00.a<BR>> > > >> PARAMETER C_EXT_RESET_HIGH = 1<BR>> > > >> PARAMETER C_CLKIN_FREQ = 100000000<BR>> > > >> PARAMETER C_CLKOUT0_FREQ = 100000000<BR>> > > >> PARAMETER C_CLKOUT0_BUF = TRUE<BR>> > > >> PARAMETER C_CLKOUT0_PHASE = 0<BR>> > > >> PARAMETER C_CLKOUT0_GROUP = DCM0<BR>> > > >> PARAMETER C_CLKOUT1_FREQ = 100000000<BR>> > > >> PARAMETER C_CLKOUT1_BUF = TRUE<BR>> > > >> PARAMETER C_CLKOUT1_PHASE = 90<BR>> > > >> PARAMETER C_CLKOUT1_GROUP = DCM0<BR>> > > >> PARAMETER C_CLKOUT2_FREQ = 300000000<BR>> > > >> PARAMETER C_CLKOUT2_BUF = TRUE<BR>> > > >> PARAMETER C_CLKOUT2_PHASE = 0<BR>> > > >> PARAMETER C_CLKOUT2_GROUP = DCM0<BR>> > > >> PARAMETER C_CLKOUT3_FREQ = 200000000<BR>> > > >> PARAMETER C_CLKOUT3_BUF = TRUE<BR>> > > >> PARAMETER C_CLKOUT3_PHASE = 0<BR>> > > >> PARAMETER C_CLKOUT3_GROUP = NONE<BR>> > > >> PARAMETER C_CLKOUT4_FREQ = 125000000<BR>> > > >> PARAMETER C_CLKOUT4_BUF = TRUE<BR>> > > >> PARAMETER C_CLKOUT4_PHASE = 0<BR>> > > >> PARAMETER C_CLKOUT4_GROUP = NONE<BR>> > > >> PORT CLKOUT0 = sys_clk_s<BR>> > > >> PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s<BR>> > > >> PORT CLKOUT2 = proc_clk_s<BR>> > > >> PORT CLKOUT3 = clk_200mhz_s<BR>> > > >> PORT CLKOUT4 = temac_clk_s<BR>> > > >> PORT CLKIN = dcm_clk_s<BR>> > > >> PORT LOCKED = Dcm_all_locked<BR>> > > >> PORT RST = net_gnd<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN proc_sys_reset<BR>> > > >> PARAMETER INSTANCE = proc_sys_reset_0<BR>> > > >> PARAMETER HW_VER = 2.00.a<BR>> > > >> PARAMETER C_EXT_RESET_HIGH = 0<BR>> > > >> BUS_INTERFACE RESETPPC0 = ppc_reset_bus<BR>> > > >> PORT Slowest_sync_clk = sys_clk_s<BR>> > > >> PORT Dcm_locked = Dcm_all_locked<BR>> > > >> PORT Ext_Reset_In = sys_rst_s<BR>> > > >> PORT Bus_Struct_Reset = sys_bus_reset<BR>> > > >> PORT Peripheral_Reset = sys_periph_reset<BR>> > > >> END<BR>> > > >><BR>> > > >> BEGIN xps_intc<BR>> > > >> PARAMETER INSTANCE = xps_intc_0<BR>> > > >> PARAMETER HW_VER = 1.00.a<BR>> > > >> PARAMETER C_BASEADDR = 0x81800000<BR>> > > >> PARAMETER C_HIGHADDR = 0x8180ffff<BR>> > > >> BUS_INTERFACE SPLB = plb<BR>> > > >> PORT Irq = EICC405EXTINPUTIRQ<BR>> > > >> PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &<BR>> > > IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &<BR>> > > TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &<BR>> > > DDR_SDRAM_SDMA2_Tx_IntOut<BR>> > > >> END<BR>> > > >><BR>> > > >><BR>> > > >><BR>> > > >> #address-cells = <1>;<BR>> > > >> #size-cells = <1>;<BR>> > > >> compatible = "xlnx,virtex";<BR>> > > >> model = "testing";<BR>> > > >> DDR_SDRAM: memory@0 {<BR>> > > >> device_type = "memory";<BR>> > > >> reg = < 0 8000000 >;<BR>> > > >> } ;<BR>> > > >> chosen {<BR>> > > >> bootargs = "console=ttyS0,9600 ip=on<BR>> > > nfsroot=172.16.40.76:/v2pclients/jhl26,tcp";<BR>> > > >> linux,stdout-path = "/plb@0/serial@83e00000";<BR>> > > >> } ;<BR>> > > >> cpus {<BR>> > > >> #address-cells = <1>;<BR>> > > >> #cpus = <1>;<BR>> > > >> #size-cells = <0>;<BR>> > > >> ppc405_0: cpu@0 {<BR>> > > >> clock-frequency = <11e1a300>;<BR>> > > >> compatible = "PowerPC,405", "ibm,ppc405";<BR>> > > >> d-cache-line-size = <20>;<BR>> > > >> d-cache-size = <4000>;<BR>> > > >> device_type = "cpu";<BR>> > > >> i-cache-line-size = <20>;<BR>> > > >> i-cache-size = <4000>;<BR>> > > >> model = "PowerPC,405";<BR>> > > >> reg = <0>;<BR>> > > >> timebase-frequency = <11e1a300>;<BR>> > > >> xlnx,apu-control = <de00>;<BR>> > > >> xlnx,apu-udi-1 = <a18983>;<BR>> > > >> xlnx,apu-udi-2 = <a38983>;<BR>> > > >> xlnx,apu-udi-3 = <a589c3>;<BR>> > > >> xlnx,apu-udi-4 = <a789c3>;<BR>> > > >> xlnx,apu-udi-5 = <a98c03>;<BR>> > > >> xlnx,apu-udi-6 = <ab8c03>;<BR>> > > >> xlnx,apu-udi-7 = <ad8c43>;<BR>> > > >> xlnx,apu-udi-8 = <af8c43>;<BR>> > > >> xlnx,deterministic-mult = <0>;<BR>> > > >> xlnx,disable-operand-forwarding = <1>;<BR>> > > >> xlnx,fastest-plb-clock = "DPLB0";<BR>> > > >> xlnx,generate-plb-timespecs = <1>;<BR>> > > >> xlnx,mmu-enable = <1>;<BR>> > > >> xlnx,pvr-high = <0>;<BR>> > > >> xlnx,pvr-low = <0>;<BR>> > > >> } ;<BR>> > > >> } ;<BR>> > > >> plb: plb@0 {<BR>> > > >> #address-cells = <1>;<BR>> > > >> #size-cells = <1>;<BR>> > > >> compatible = "xlnx,plb-v46-1.02.a";<BR>> > > >> ranges ;<BR>> > > >> IIC_EEPROM: i2c@81600000 {<BR>> > > >> compatible = "xlnx,xps-iic-2.00.a";<BR>> > > >> interrupt-parent = <&xps_intc_0>;<BR>> > > >> interrupts = < 4 2 >;<BR>> > > >> reg = < 81600000 10000 >;<BR>> > > >> xlnx,clk-freq = <5f5e100>;<BR>> > > >> xlnx,family = "virtex4";<BR>> > > >> xlnx,gpo-width = <1>;<BR>> > > >> xlnx,iic-freq = <186a0>;<BR>> > > >> xlnx,scl-inertial-delay = <0>;<BR>> > > >> xlnx,sda-inertial-delay = <0>;<BR>> > > >> xlnx,ten-bit-adr = <0>;<BR>> > > >> } ;<BR>> > > >> LEDs_4Bit: gpio@81400000 {<BR>> > > >> compatible = "xlnx,xps-gpio-1.00.a";<BR>> > > >> interrupt-parent = <&xps_intc_0>;<BR>> > > >> interrupts = < 5 2 >;<BR>> > > >> reg = < 81400000 10000 >;<BR>> > > >> xlnx,all-inputs = <0>;<BR>> > > >> xlnx,all-inputs-2 = <0>;<BR>> > > >> xlnx,dout-default = <0>;<BR>> > > >> xlnx,dout-default-2 = <0>;<BR>> > > >> xlnx,family = "virtex4";<BR>> > > >> xlnx,gpio-width = <4>;<BR>> > > >> xlnx,interrupt-present = <1>;<BR>> > > >> xlnx,is-bidir = <1>;<BR>> > > >> xlnx,is-bidir-2 = <1>;<BR>> > > >> xlnx,is-dual = <0>;<BR>> > > >> xlnx,tri-default = <ffffffff>;<BR>> > > >> xlnx,tri-default-2 = <ffffffff>;<BR>> > > >> } ;<BR>> > > >> RS232_Uart: serial@83e00000 {<BR>> > > >> compatible = "xlnx,xps-uart16550-2.00.a";<BR>> > > >> // compatible = "ns16550";<BR>> > > >> device_type = "serial";<BR>> > > >> interrupt-parent = <&xps_intc_0>;<BR>> > > >> interrupts = < 6 2 >;<BR>> > > >> reg = < 83e00000 10000 >;<BR>> > > >> current-speed = <d#9600>;<BR>> > > >> clock-frequency = <d#100000000>; /* added<BR>> > > by jhl */<BR>> > > >> reg-shift = <2>;<BR>> > > >> xlnx,family = "virtex4";<BR>> > > >> xlnx,has-external-rclk = <0>;<BR>> > > >> xlnx,has-external-xin = <0>;<BR>> > > >> xlnx,is-a-16550 = <1>;<BR>> > > >> } ;<BR>> > > >> SysACE_CompactFlash: sysace@83600000 {<BR>> > > >> compatible = "xlnx,xps-sysace-1.00.a";<BR>> > > >> interrupt-parent = <&xps_intc_0>;<BR>> > > >> interrupts = < 3 2 >;<BR>> > > >> reg = < 83600000 10000 >;<BR>> > > >> xlnx,family = "virtex4";<BR>> > > >> xlnx,mem-width = <10>;<BR>> > > >> } ;<BR>> > > >> TriMode_MAC_GMII: xps-ll-temac@81c00000 {<BR>> > > >> #address-cells = <1>;<BR>> > > >> #size-cells = <1>;<BR>> > > >> compatible = "xlnx,compound";<BR>> > > >> ethernet@81c00000 {<BR>> > > >> compatible = "xlnx,xps-ll-temac-<BR>> > > 1.01.a";<BR>> > > >> device_type = "network";<BR>> > > >> interrupt-parent =<BR>> > > <&xps_intc_0>;<BR>> > > >> interrupts = < 2 2 >;<BR>> > > >> llink-connected = <&PIM2>;<BR>> > > >> local-mac-address = [ 02 00 00<BR>> > > 00 00 01 ];<BR>> > > >> reg = < 81c00000 40 >;<BR>> > > >> xlnx,bus2core-clk-ratio = <1>;<BR>> > > >> xlnx,phy-type = <1>;<BR>> > > >> xlnx,phyaddr = <1>;<BR>> > > >> xlnx,rxcsum = <0>;<BR>> > > >> xlnx,rxfifo = <1000>;<BR>> > > >> xlnx,temac-type = <1>;<BR>> > > >> xlnx,txcsum = <0>;<BR>> > > >> xlnx,txfifo = <1000>;<BR>> > > >> } ;<BR>> > > >> } ;<BR>> > > >> mpmc@0 {<BR>> > > >> #address-cells = <1>;<BR>> > > >> #size-cells = <1>;<BR>> > > >> compatible = "xlnx,mpmc-4.00.a";<BR>> > > >> PIM2: sdma@84600100 {<BR>> > > >> compatible = "xlnx,ll-dma-<BR>> > > 1.00.a";<BR>> > > >> interrupt-parent =<BR>> > > <&xps_intc_0>;<BR>> > > >> interrupts = < 1 2 0 2 >;<BR>> > > >> reg = < 84600100 80 >;<BR>> > > >> } ;<BR>> > > >> } ;<BR>> > > >> xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {<BR>> > > >> compatible = "xlnx,xps-bram-if-cntlr-<BR>> > > 1.00.a";<BR>> > > >> reg = < ffffe000 2000 >;<BR>> > > >> xlnx,family = "virtex4";<BR>> > > >> } ;<BR>> > > >> xps_intc_0: interrupt-controller@81800000 {<BR>> > > >> #interrupt-cells = <2>;<BR>> > > >> compatible = "xlnx,xps-intc-1.00.a";<BR>> > > >> interrupt-controller ;<BR>> > > >> reg = < 81800000 10000 >;<BR>> > > >> xlnx,num-intr-inputs = <7>;<BR>> > > >> } ;<BR>> > > >> } ;<BR>> > > >> ppc405_0_dplb1: plb@1 {<BR>> > > >> #address-cells = <1>;<BR>> > > >> #size-cells = <1>;<BR>> > > >> compatible = "xlnx,plb-v46-1.02.a";<BR>> > > >> ranges ;<BR>> > > >> } ;<BR>> > > >> } ;<BR>> > > >><BR>> > > >><BR>> > > >><BR>> > > >> -----Original Message-----<BR>> > > >> From: Magnus Hjorth [mailto:mh@omnisys.se]<BR>> > > >> Sent: Saturday, March 29, 2008 6:54 AM<BR>> > > >> To: git<BR>> > > >> Cc: linuxppc-embedded@ozlabs.org<BR>> > > >> Subject: Xilinx LLTEMAC driver issues<BR>> > > >><BR>> > > >> Hi,<BR>> > > >><BR>> > > >> I'm having some networking troubles with the Xilinx LLTEMAC driver from<BR>> > the<BR>> > > >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,<BR>> > > >> xps_ll_temac v1.00.b<BR>> > > >><BR>> > > >> The weird thing is, that it sort of half works. It successfully makes a<BR>> > DHCP<BR>> > > >> request and gets its IP address. I tried setting up a tftpd server, and<BR>> > I can<BR>> > > >> see UDP requests coming in but the response doesn't seem to come out. I<BR>> > also<BR>> > > >> tried running a TCP server on the board, and it can see and accept<BR>> > incoming<BR>> > > >> connections but after that no data seems to get through. I can ping out<BR>> > and<BR>> > > >> get around 40% packet loss.<BR>> > > >><BR>> > > >> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma<BR>> > > >> interrupts. No eth0 interrupts but that seems to be OK judging by the<BR>> > driver<BR>> > > >> source comments. Ifconfig shows no collistions, no dropped packets, no<BR>> > > errors,<BR>> > > >> so the system seems to think that everything is OK.<BR>> > > >><BR>> > > >> Clues anyone? I'm starting to run out of ideas...<BR>> > > >><BR>> > > >> Best regards,<BR>> > > >> Magnus<BR>> > > >><BR>> > > >><BR>> > > >> --<BR>> > > >><BR>> > > >> Magnus Hjorth, M.Sc.<BR>> > > >> Omnisys Instruments AB<BR>> > > >> Gruvgatan 8<BR>> > > >> SE-421 30 Västra Frölunda, SWEDEN<BR>> > > >> Phone: +46 31 734 34 09<BR>> > > >> Fax: +46 31 734 34 29<BR>> > > >> http://www.omnisys.se<BR>> > > >><BR>> > > ><BR>> > > > _______________________________________________<BR>> > > > Linuxppc-embedded mailing list<BR>> > > > Linuxppc-embedded@ozlabs.org<BR>> > > > https://ozlabs.org/mailman/listinfo/linuxppc-embedded<BR>> > _______________________________________________<BR>> > Linuxppc-embedded mailing list<BR>> > Linuxppc-embedded@ozlabs.org<BR>> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded<BR>> ><BR>> ><BR>> > --<BR>> > Johann Baudy<BR>> > johaahn@gmail.com<BR>> > ________________________________<BR>> > 用 Windows Live Spaces 展示个性自我，与好友分享生活！ 了解更多信息！<BR>> <BR>> <BR>> <BR>> -- <BR>> Johann Baudy<BR>> johaahn@gmail.com<BR><BR><br /><hr />用 Windows Live Spaces 展示个性自我，与好友分享生活！ <a href='http://spaces.live.com/?page=HP' target='_new'>了解更多信息！</a></body>
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