I've solved this checksum offloading issue with this below patch.<br>It may help, if you need performance. It certainly needs review but it works on my side.<br><br>--- xilinxgit/drivers/net/xilinx<div id="1fiv" class="ArwC7c ckChnd">
_lltemac/xlltemac_main.c.orig 2008-03-21 09:11:43.000000000 +0100<br>
+++ xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c 2008-03-21 09:24:23.000000000 +0100<br>@@ -133,7 +133,7 @@<br> (XLlDma_mBdRead((BdPtr), XLLDMA_BD_STSCTRL_USR0_OFFSET)) & 0xFFFFFFFE )<br> <br> #define BdCsumSetup(BdPtr, Start, Insert) \<br>
- XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 | (Insert))<br>+ XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) | (Insert))<br> <br> /* Used for debugging */<br> #define BdCsumInsert(BdPtr) \<br>
@@ -1540,7 +1541,7 @@ static int xenet_DmaSend_internal(struct<br> /*<br> * if tx checksum offloading is enabled, when the ethernet stack<br>
* wants us to perform the checksum in hardware,<br>- * skb->ip_summed is CHECKSUM_COMPLETE. Otherwise skb->ip_summed is<br>+ * skb->ip_summed is CHECKSUM_PARTIAL. Otherwise skb->ip_summed is<br>
* CHECKSUM_NONE, meaning the checksum is already done, or<br>
* CHECKSUM_UNNECESSARY, meaning checksumming is turned off (e.g.<br> * loopback interface)<br>@@ -1565,9 +1566,11 @@ static int xenet_DmaSend_internal(struct<br> * skb_transport_header(skb) points to the beginning of the ip header<br>
*<br> */<br>- if (skb->ip_summed == CHECKSUM_COMPLETE) {<br>+ if (skb->ip_summed == CHECKSUM_PARTIAL) {<br>+<br>+ unsigned int csum_start_off = skb_transport_offset(skb);<br>+ unsigned int csum_index_off = csum_start_off + skb->csum_offset;<br>
<br>- unsigned char *raw = skb_transport_header(skb);<br> #if 0<br> {<br> unsigned int csum = _xenet_tx_csum(skb);<br>@@ -1578,9 +1581,8 @@ static int xenet_DmaSend_internal(struct<br> }<br>
#else<br> BdCsumEnable(bd_ptr);<br>- BdCsumSetup(bd_ptr, raw - skb->data,<br>- (raw - skb->data) + skb->csum);<br>-<br>+ BdCsumSetup(bd_ptr, csum_start_off,<br>+ csum_index_off);<br>
#endif<br> lp->tx_hw_csums++;<br> }<br>@@ -3277,7 +3279,7 @@ static int __devinit xtenet_of_probe(str<br> struct resource *r_irq = &r_irq_struct; /* Interrupt resources */<br> struct resource *r_mem = &r_mem_struct; /* IO mem resources */<br>
struct xlltemac_platform_data *pdata = &pdata_struct;<br>- void *mac_address;<br>+ const void *mac_address;<br> int rc = 0;<br> const phandle *llink_connected_handle;<br> struct device_node *llink_connected_node;</div>
<br><br><div class="gmail_quote">On Mon, Mar 31, 2008 at 11:10 AM, Magnus Hjorth <<a href="mailto:mh@omnisys.se">mh@omnisys.se</a>> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Deactivating checksum offloading helped a lot! I still have some packet loss and not the best performance (TFTP transfer about 100 kbyte/s) but at least it works.<br>
<br>
Thanks!<br>
<font color="#888888"><br>
//Magnus<br>
</font><div><div></div><div class="Wj3C7c"><br>
> -----Original Message-----<br>
> From: rza1 [mailto:<a href="mailto:rza1@so-logic.net">rza1@so-logic.net</a>]<br>
> Sent: den 31 mars 2008 11:14<br>
> To: Magnus Hjorth<br>
> Cc: John Linn; git; <a href="mailto:linuxppc-embedded@ozlabs.org">linuxppc-embedded@ozlabs.org</a><br>
> Subject: Re: Xilinx LLTEMAC driver issues<br>
><br>
> Hi Magnus,<br>
><br>
> 1.<br>
> I am using nearly the same versions then you and got the same problems<br>
> too ;-).<br>
> I think there are some problems with the checksum offloading.<br>
> Try to sniff the some packages (e.g. wireshark)...<br>
> For me ICMP (ping) worked but udp and tcp not (because off a wrong<br>
> checksum in the transport layer).<br>
> A quick solution is to just deactivate checksum offloading.<br>
><br>
> 2.<br>
> I remember some problems with Virtex-4 presamples too.<br>
> There where problems with the hard-temac wrapper. You had to use 1.00.a<br>
> and not b version.<br>
> But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.<br>
><br>
> all the best,<br>
> Robert<br>
><br>
> Magnus Hjorth wrote:<br>
> > Hi John,<br>
> ><br>
> > Thanks for the very fast reply! Right now I'm not at work so I don't<br>
> > have the board or EDK here to test anything.<br>
> ><br>
> > I'm using checksum offload, but I don't know if DRE is enabled or not. I<br>
> > can't recall seeing any setting to enable/disable DRE..<br>
> ><br>
> > A few things that crossed my mind:<br>
> ><br>
> > Last year I did a design with EDK 8.2, back then there was an issue with<br>
> > the ML403 boards having an old revision of the FPGA which wasn't<br>
> > compatible with some versions of the IP core. There are no such version<br>
> > issues with the xps_ll_temac?<br>
> ><br>
> > I don't think that I had phy-addr set in the DTS file. Will test that on<br>
> > Monday.<br>
> ><br>
> > Best regards,<br>
> > Magnus<br>
> ><br>
> ><br>
> > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:<br>
> ><br>
> >> Hi Magnus,<br>
> >><br>
> >> Sorry to hear you're having problems with it.<br>
> >><br>
> >> I am doing testing on an ML405 which is the same board but with a bigger<br>
> FPGA, but with ppc arch and I don't see this issue. I have done limited testing<br>
> with powerpc arch and the LL TEMAC, but I didn't see this issue there either.<br>
> Powerpc arch is definitely less mature in my experience than the ppc arch. I'll<br>
> do a quick test with my powerpc arch and make sure again I'm not seeing it.<br>
> >><br>
> >> My kernel is from the Xilinx Git tree, but there have been a number of<br>
> changes we have pushed out so I don't know how long ago you pulled from the Git<br>
> tree.<br>
> >><br>
> >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a so<br>
> it's a little newer. I reviewed the change log for the LL TEMAC and don't see<br>
> any big problems that were fixed in the newer versions, more new features. I'll<br>
> check with some others here to see if I missed something there.<br>
> >><br>
> >> I am using DMA also, but no DRE or checksum offload. You didn't say anything<br>
> about those. I'm going to insert my mhs file that describes my system to let you<br>
> compare your system configuration. It's not clear to me yet if you have a h/w or<br>
> s/w problem.<br>
> >><br>
> >> I'll also insert some of my device tree with the LL TEMAC so you can compare<br>
> (ignore 16550 stuff as we are still working on that).<br>
> >><br>
> >> Since you can't ping reliably I would probably focus on that since it's<br>
> simpler than the other issues you're seeing.<br>
> >><br>
> >> Thanks,<br>
> >> John<br>
> >><br>
> >><br>
> >><br>
> >> #<br>
> ##############################################################################<br>
> >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build<br>
> EDK_K_SP1.1<br>
> >> # Thu Feb 14 14:11:12 2008<br>
> >> # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1<br>
> >> # Family: virtex4<br>
> >> # Device: xc4vfx20<br>
> >> # Package: ff672<br>
> >> # Speed Grade: -10<br>
> >> # Processor: ppc405_0<br>
> >> # Processor clock frequency: 300.00 MHz<br>
> >> # Bus clock frequency: 100.00 MHz<br>
> >> # On Chip Memory : 8 KB<br>
> >> # Total Off Chip Memory : 128 MB<br>
> >> # - DDR_SDRAM = 128 MB<br>
> >> #<br>
> ##############################################################################<br>
> >> PARAMETER VERSION = 2.1.0<br>
> >><br>
> >><br>
> >> PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I<br>
> >> PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O<br>
> >> PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC<br>
> = [0:3]<br>
> >> PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO<br>
> >> PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O<br>
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =<br>
> fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC<br>
> = [12:0]<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR<br>
> = O, VEC = [1:0]<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC =<br>
> [3:0]<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC =<br>
> [3:0]<br>
> >> PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC =<br>
> [31:0]<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I<br>
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I<br>
> >> PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =<br>
> fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I<br>
> >> PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0,<br>
> DIR = IO<br>
> >> PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0, DIR<br>
> = O<br>
> >> PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =<br>
> fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O<br>
> >> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000<br>
> >> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST<br>
> >><br>
> >><br>
> >> BEGIN ppc405_virtex4<br>
> >> PARAMETER INSTANCE = ppc405_0<br>
> >> PARAMETER HW_VER = 2.01.a<br>
> >> PARAMETER C_FASTEST_PLB_CLOCK = DPLB1<br>
> >> PARAMETER C_IDCR_BASEADDR = 0b0100000000<br>
> >> PARAMETER C_IDCR_HIGHADDR = 0b0111111111<br>
> >> BUS_INTERFACE JTAGPPC = jtagppc_0_0<br>
> >> BUS_INTERFACE IPLB0 = plb<br>
> >> BUS_INTERFACE DPLB0 = plb<br>
> >> BUS_INTERFACE IPLB1 = ppc405_0_iplb1<br>
> >> BUS_INTERFACE DPLB1 = ppc405_0_dplb1<br>
> >> BUS_INTERFACE RESETPPC = ppc_reset_bus<br>
> >> PORT CPMC405CLOCK = proc_clk_s<br>
> >> PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ<br>
> >> END<br>
> >><br>
> >> BEGIN jtagppc_cntlr<br>
> >> PARAMETER INSTANCE = jtagppc_0<br>
> >> PARAMETER HW_VER = 2.01.a<br>
> >> BUS_INTERFACE JTAGPPC0 = jtagppc_0_0<br>
> >> END<br>
> >><br>
> >> BEGIN plb_v46<br>
> >> PARAMETER INSTANCE = plb<br>
> >> PARAMETER C_DCR_INTFCE = 0<br>
> >> PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100<br>
> >> PARAMETER HW_VER = 1.02.a<br>
> >> PORT PLB_Clk = sys_clk_s<br>
> >> PORT SYS_Rst = sys_bus_reset<br>
> >> END<br>
> >><br>
> >> BEGIN xps_bram_if_cntlr<br>
> >> PARAMETER INSTANCE = xps_bram_if_cntlr_1<br>
> >> PARAMETER HW_VER = 1.00.a<br>
> >> PARAMETER C_SPLB_NATIVE_DWIDTH = 64<br>
> >> PARAMETER C_BASEADDR = 0xffffe000<br>
> >> PARAMETER C_HIGHADDR = 0xffffffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port<br>
> >> END<br>
> >><br>
> >> BEGIN bram_block<br>
> >> PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram<br>
> >> PARAMETER HW_VER = 1.00.a<br>
> >> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port<br>
> >> END<br>
> >><br>
> >> BEGIN xps_uart16550<br>
> >> PARAMETER INSTANCE = RS232_Uart<br>
> >> PARAMETER HW_VER = 2.00.a<br>
> >> PARAMETER C_IS_A_16550 = 1<br>
> >> PARAMETER C_BASEADDR = 0x83e00000<br>
> >> PARAMETER C_HIGHADDR = 0x83e0ffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> PORT sin = fpga_0_RS232_Uart_sin<br>
> >> PORT sout = fpga_0_RS232_Uart_sout<br>
> >> PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt<br>
> >> END<br>
> >><br>
> >> BEGIN xps_gpio<br>
> >> PARAMETER INSTANCE = LEDs_4Bit<br>
> >> PARAMETER HW_VER = 1.00.a<br>
> >> PARAMETER C_INTERRUPT_PRESENT = 1<br>
> >> PARAMETER C_GPIO_WIDTH = 4<br>
> >> PARAMETER C_IS_DUAL = 0<br>
> >> PARAMETER C_IS_BIDIR = 1<br>
> >> PARAMETER C_ALL_INPUTS = 0<br>
> >> PARAMETER C_BASEADDR = 0x81400000<br>
> >> PARAMETER C_HIGHADDR = 0x8140ffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO<br>
> >> PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt<br>
> >> END<br>
> >><br>
> >> BEGIN xps_iic<br>
> >> PARAMETER INSTANCE = IIC_EEPROM<br>
> >> PARAMETER HW_VER = 2.00.a<br>
> >> PARAMETER C_CLK_FREQ = 100000000<br>
> >> PARAMETER C_IIC_FREQ = 100000<br>
> >> PARAMETER C_TEN_BIT_ADR = 0<br>
> >> PARAMETER C_BASEADDR = 0x81600000<br>
> >> PARAMETER C_HIGHADDR = 0x8160ffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> PORT Scl = fpga_0_IIC_EEPROM_Scl<br>
> >> PORT Sda = fpga_0_IIC_EEPROM_Sda<br>
> >> PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt<br>
> >> END<br>
> >><br>
> >> BEGIN xps_sysace<br>
> >> PARAMETER INSTANCE = SysACE_CompactFlash<br>
> >> PARAMETER HW_VER = 1.00.a<br>
> >> PARAMETER C_MEM_WIDTH = 16<br>
> >> PARAMETER C_BASEADDR = 0x83600000<br>
> >> PARAMETER C_HIGHADDR = 0x8360ffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK<br>
> >> PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split<br>
> >> PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD<br>
> >> PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN<br>
> >> PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN<br>
> >> PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN<br>
> >> PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ<br>
> >> PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ<br>
> >> END<br>
> >><br>
> >> BEGIN mpmc<br>
> >> PARAMETER INSTANCE = DDR_SDRAM<br>
> >> PARAMETER HW_VER = 4.00.a<br>
> >> PARAMETER C_NUM_PORTS = 3<br>
> >> PARAMETER C_MEM_PARTNO = HYB25D512160BE-5<br>
> >> PARAMETER C_MEM_DATA_WIDTH = 32<br>
> >> PARAMETER C_MEM_DQS_WIDTH = 4<br>
> >> PARAMETER C_MEM_DM_WIDTH = 4<br>
> >> PARAMETER C_MEM_TYPE = DDR<br>
> >> PARAMETER C_NUM_IDELAYCTRL = 2<br>
> >> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2<br>
> >> PARAMETER C_PIM0_BASETYPE = 2<br>
> >> PARAMETER C_PIM1_BASETYPE = 2<br>
> >> PARAMETER C_PIM2_BASETYPE = 3<br>
> >> PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000<br>
> >> PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1<br>
> >> PARAMETER C_MPMC_BASEADDR = 0x00000000<br>
> >> PARAMETER C_MPMC_HIGHADDR = 0x07ffffff<br>
> >> PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000<br>
> >> PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff<br>
> >> BUS_INTERFACE SPLB0 = ppc405_0_iplb1<br>
> >> BUS_INTERFACE SPLB1 = ppc405_0_dplb1<br>
> >> BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0<br>
> >> BUS_INTERFACE SDMA_CTRL2 = plb<br>
> >> PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr<br>
> >> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr<br>
> >> PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n<br>
> >> PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE<br>
> >> PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n<br>
> >> PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n<br>
> >> PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n<br>
> >> PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM<br>
> >> PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS<br>
> >> PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ<br>
> >> PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk<br>
> >> PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n<br>
> >> PORT MPMC_Clk0 = sys_clk_s<br>
> >> PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s<br>
> >> PORT SDMA2_Clk = sys_clk_s<br>
> >> PORT MPMC_Clk_200MHz = clk_200mhz_s<br>
> >> PORT MPMC_Rst = sys_periph_reset<br>
> >> PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut<br>
> >> PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut<br>
> >> END<br>
> >><br>
> >> BEGIN xps_ll_temac<br>
> >> PARAMETER INSTANCE = TriMode_MAC_GMII<br>
> >> PARAMETER HW_VER = 1.01.a<br>
> >> PARAMETER C_SPLB_CLK_PERIOD_PS = 10000<br>
> >> PARAMETER C_PHY_TYPE = 1<br>
> >> PARAMETER C_NUM_IDELAYCTRL = 4<br>
> >> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-<br>
> IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3<br>
> >> PARAMETER C_TEMAC_TYPE = 1<br>
> >> PARAMETER C_BUS2CORE_CLK_RATIO = 1<br>
> >> PARAMETER C_BASEADDR = 0x81c00000<br>
> >> PARAMETER C_HIGHADDR = 0x81c0ffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0<br>
> >> PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0<br>
> >> PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0<br>
> >> PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0<br>
> >> PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0<br>
> >> PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0<br>
> >> PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0<br>
> >> PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0<br>
> >> PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0<br>
> >> PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0<br>
> >> PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0<br>
> >> PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0<br>
> >> PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n<br>
> >> PORT GTX_CLK_0 = temac_clk_s<br>
> >> PORT REFCLK = clk_200mhz_s<br>
> >> PORT LlinkTemac0_CLK = sys_clk_s<br>
> >> PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt<br>
> >> END<br>
> >><br>
> >> BEGIN util_bus_split<br>
> >> PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0<br>
> >> PARAMETER HW_VER = 1.00.a<br>
> >> PARAMETER C_SIZE_IN = 7<br>
> >> PARAMETER C_LEFT_POS = 0<br>
> >> PARAMETER C_SPLIT = 6<br>
> >> PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split<br>
> >> PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA<br>
> >> END<br>
> >><br>
> >> BEGIN plb_v46<br>
> >> PARAMETER INSTANCE = ppc405_0_iplb1<br>
> >> PARAMETER HW_VER = 1.02.a<br>
> >> PORT PLB_Clk = sys_clk_s<br>
> >> PORT SYS_Rst = sys_bus_reset<br>
> >> END<br>
> >><br>
> >> BEGIN plb_v46<br>
> >> PARAMETER INSTANCE = ppc405_0_dplb1<br>
> >> PARAMETER HW_VER = 1.02.a<br>
> >> PORT PLB_Clk = sys_clk_s<br>
> >> PORT SYS_Rst = sys_bus_reset<br>
> >> END<br>
> >><br>
> >> BEGIN clock_generator<br>
> >> PARAMETER INSTANCE = clock_generator_0<br>
> >> PARAMETER HW_VER = 2.00.a<br>
> >> PARAMETER C_EXT_RESET_HIGH = 1<br>
> >> PARAMETER C_CLKIN_FREQ = 100000000<br>
> >> PARAMETER C_CLKOUT0_FREQ = 100000000<br>
> >> PARAMETER C_CLKOUT0_BUF = TRUE<br>
> >> PARAMETER C_CLKOUT0_PHASE = 0<br>
> >> PARAMETER C_CLKOUT0_GROUP = DCM0<br>
> >> PARAMETER C_CLKOUT1_FREQ = 100000000<br>
> >> PARAMETER C_CLKOUT1_BUF = TRUE<br>
> >> PARAMETER C_CLKOUT1_PHASE = 90<br>
> >> PARAMETER C_CLKOUT1_GROUP = DCM0<br>
> >> PARAMETER C_CLKOUT2_FREQ = 300000000<br>
> >> PARAMETER C_CLKOUT2_BUF = TRUE<br>
> >> PARAMETER C_CLKOUT2_PHASE = 0<br>
> >> PARAMETER C_CLKOUT2_GROUP = DCM0<br>
> >> PARAMETER C_CLKOUT3_FREQ = 200000000<br>
> >> PARAMETER C_CLKOUT3_BUF = TRUE<br>
> >> PARAMETER C_CLKOUT3_PHASE = 0<br>
> >> PARAMETER C_CLKOUT3_GROUP = NONE<br>
> >> PARAMETER C_CLKOUT4_FREQ = 125000000<br>
> >> PARAMETER C_CLKOUT4_BUF = TRUE<br>
> >> PARAMETER C_CLKOUT4_PHASE = 0<br>
> >> PARAMETER C_CLKOUT4_GROUP = NONE<br>
> >> PORT CLKOUT0 = sys_clk_s<br>
> >> PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s<br>
> >> PORT CLKOUT2 = proc_clk_s<br>
> >> PORT CLKOUT3 = clk_200mhz_s<br>
> >> PORT CLKOUT4 = temac_clk_s<br>
> >> PORT CLKIN = dcm_clk_s<br>
> >> PORT LOCKED = Dcm_all_locked<br>
> >> PORT RST = net_gnd<br>
> >> END<br>
> >><br>
> >> BEGIN proc_sys_reset<br>
> >> PARAMETER INSTANCE = proc_sys_reset_0<br>
> >> PARAMETER HW_VER = 2.00.a<br>
> >> PARAMETER C_EXT_RESET_HIGH = 0<br>
> >> BUS_INTERFACE RESETPPC0 = ppc_reset_bus<br>
> >> PORT Slowest_sync_clk = sys_clk_s<br>
> >> PORT Dcm_locked = Dcm_all_locked<br>
> >> PORT Ext_Reset_In = sys_rst_s<br>
> >> PORT Bus_Struct_Reset = sys_bus_reset<br>
> >> PORT Peripheral_Reset = sys_periph_reset<br>
> >> END<br>
> >><br>
> >> BEGIN xps_intc<br>
> >> PARAMETER INSTANCE = xps_intc_0<br>
> >> PARAMETER HW_VER = 1.00.a<br>
> >> PARAMETER C_BASEADDR = 0x81800000<br>
> >> PARAMETER C_HIGHADDR = 0x8180ffff<br>
> >> BUS_INTERFACE SPLB = plb<br>
> >> PORT Irq = EICC405EXTINPUTIRQ<br>
> >> PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &<br>
> IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &<br>
> TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &<br>
> DDR_SDRAM_SDMA2_Tx_IntOut<br>
> >> END<br>
> >><br>
> >><br>
> >><br>
> >> #address-cells = <1>;<br>
> >> #size-cells = <1>;<br>
> >> compatible = "xlnx,virtex";<br>
> >> model = "testing";<br>
> >> DDR_SDRAM: memory@0 {<br>
> >> device_type = "memory";<br>
> >> reg = < 0 8000000 >;<br>
> >> } ;<br>
> >> chosen {<br>
> >> bootargs = "console=ttyS0,9600 ip=on<br>
> nfsroot=172.16.40.76:/v2pclients/jhl26,tcp";<br>
> >> linux,stdout-path = "/plb@0/serial@83e00000";<br>
> >> } ;<br>
> >> cpus {<br>
> >> #address-cells = <1>;<br>
> >> #cpus = <1>;<br>
> >> #size-cells = <0>;<br>
> >> ppc405_0: cpu@0 {<br>
> >> clock-frequency = <11e1a300>;<br>
> >> compatible = "PowerPC,405", "ibm,ppc405";<br>
> >> d-cache-line-size = <20>;<br>
> >> d-cache-size = <4000>;<br>
> >> device_type = "cpu";<br>
> >> i-cache-line-size = <20>;<br>
> >> i-cache-size = <4000>;<br>
> >> model = "PowerPC,405";<br>
> >> reg = <0>;<br>
> >> timebase-frequency = <11e1a300>;<br>
> >> xlnx,apu-control = <de00>;<br>
> >> xlnx,apu-udi-1 = <a18983>;<br>
> >> xlnx,apu-udi-2 = <a38983>;<br>
> >> xlnx,apu-udi-3 = <a589c3>;<br>
> >> xlnx,apu-udi-4 = <a789c3>;<br>
> >> xlnx,apu-udi-5 = <a98c03>;<br>
> >> xlnx,apu-udi-6 = <ab8c03>;<br>
> >> xlnx,apu-udi-7 = <ad8c43>;<br>
> >> xlnx,apu-udi-8 = <af8c43>;<br>
> >> xlnx,deterministic-mult = <0>;<br>
> >> xlnx,disable-operand-forwarding = <1>;<br>
> >> xlnx,fastest-plb-clock = "DPLB0";<br>
> >> xlnx,generate-plb-timespecs = <1>;<br>
> >> xlnx,mmu-enable = <1>;<br>
> >> xlnx,pvr-high = <0>;<br>
> >> xlnx,pvr-low = <0>;<br>
> >> } ;<br>
> >> } ;<br>
> >> plb: plb@0 {<br>
> >> #address-cells = <1>;<br>
> >> #size-cells = <1>;<br>
> >> compatible = "xlnx,plb-v46-1.02.a";<br>
> >> ranges ;<br>
> >> IIC_EEPROM: i2c@81600000 {<br>
> >> compatible = "xlnx,xps-iic-2.00.a";<br>
> >> interrupt-parent = <&xps_intc_0>;<br>
> >> interrupts = < 4 2 >;<br>
> >> reg = < 81600000 10000 >;<br>
> >> xlnx,clk-freq = <5f5e100>;<br>
> >> xlnx,family = "virtex4";<br>
> >> xlnx,gpo-width = <1>;<br>
> >> xlnx,iic-freq = <186a0>;<br>
> >> xlnx,scl-inertial-delay = <0>;<br>
> >> xlnx,sda-inertial-delay = <0>;<br>
> >> xlnx,ten-bit-adr = <0>;<br>
> >> } ;<br>
> >> LEDs_4Bit: gpio@81400000 {<br>
> >> compatible = "xlnx,xps-gpio-1.00.a";<br>
> >> interrupt-parent = <&xps_intc_0>;<br>
> >> interrupts = < 5 2 >;<br>
> >> reg = < 81400000 10000 >;<br>
> >> xlnx,all-inputs = <0>;<br>
> >> xlnx,all-inputs-2 = <0>;<br>
> >> xlnx,dout-default = <0>;<br>
> >> xlnx,dout-default-2 = <0>;<br>
> >> xlnx,family = "virtex4";<br>
> >> xlnx,gpio-width = <4>;<br>
> >> xlnx,interrupt-present = <1>;<br>
> >> xlnx,is-bidir = <1>;<br>
> >> xlnx,is-bidir-2 = <1>;<br>
> >> xlnx,is-dual = <0>;<br>
> >> xlnx,tri-default = <ffffffff>;<br>
> >> xlnx,tri-default-2 = <ffffffff>;<br>
> >> } ;<br>
> >> RS232_Uart: serial@83e00000 {<br>
> >> compatible = "xlnx,xps-uart16550-2.00.a";<br>
> >> // compatible = "ns16550";<br>
> >> device_type = "serial";<br>
> >> interrupt-parent = <&xps_intc_0>;<br>
> >> interrupts = < 6 2 >;<br>
> >> reg = < 83e00000 10000 >;<br>
> >> current-speed = <d#9600>;<br>
> >> clock-frequency = <d#100000000>; /* added<br>
> by jhl */<br>
> >> reg-shift = <2>;<br>
> >> xlnx,family = "virtex4";<br>
> >> xlnx,has-external-rclk = <0>;<br>
> >> xlnx,has-external-xin = <0>;<br>
> >> xlnx,is-a-16550 = <1>;<br>
> >> } ;<br>
> >> SysACE_CompactFlash: sysace@83600000 {<br>
> >> compatible = "xlnx,xps-sysace-1.00.a";<br>
> >> interrupt-parent = <&xps_intc_0>;<br>
> >> interrupts = < 3 2 >;<br>
> >> reg = < 83600000 10000 >;<br>
> >> xlnx,family = "virtex4";<br>
> >> xlnx,mem-width = <10>;<br>
> >> } ;<br>
> >> TriMode_MAC_GMII: xps-ll-temac@81c00000 {<br>
> >> #address-cells = <1>;<br>
> >> #size-cells = <1>;<br>
> >> compatible = "xlnx,compound";<br>
> >> ethernet@81c00000 {<br>
> >> compatible = "xlnx,xps-ll-temac-<br>
> 1.01.a";<br>
> >> device_type = "network";<br>
> >> interrupt-parent =<br>
> <&xps_intc_0>;<br>
> >> interrupts = < 2 2 >;<br>
> >> llink-connected = <&PIM2>;<br>
> >> local-mac-address = [ 02 00 00<br>
> 00 00 01 ];<br>
> >> reg = < 81c00000 40 >;<br>
> >> xlnx,bus2core-clk-ratio = <1>;<br>
> >> xlnx,phy-type = <1>;<br>
> >> xlnx,phyaddr = <1>;<br>
> >> xlnx,rxcsum = <0>;<br>
> >> xlnx,rxfifo = <1000>;<br>
> >> xlnx,temac-type = <1>;<br>
> >> xlnx,txcsum = <0>;<br>
> >> xlnx,txfifo = <1000>;<br>
> >> } ;<br>
> >> } ;<br>
> >> mpmc@0 {<br>
> >> #address-cells = <1>;<br>
> >> #size-cells = <1>;<br>
> >> compatible = "xlnx,mpmc-4.00.a";<br>
> >> PIM2: sdma@84600100 {<br>
> >> compatible = "xlnx,ll-dma-<br>
> 1.00.a";<br>
> >> interrupt-parent =<br>
> <&xps_intc_0>;<br>
> >> interrupts = < 1 2 0 2 >;<br>
> >> reg = < 84600100 80 >;<br>
> >> } ;<br>
> >> } ;<br>
> >> xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {<br>
> >> compatible = "xlnx,xps-bram-if-cntlr-<br>
> 1.00.a";<br>
> >> reg = < ffffe000 2000 >;<br>
> >> xlnx,family = "virtex4";<br>
> >> } ;<br>
> >> xps_intc_0: interrupt-controller@81800000 {<br>
> >> #interrupt-cells = <2>;<br>
> >> compatible = "xlnx,xps-intc-1.00.a";<br>
> >> interrupt-controller ;<br>
> >> reg = < 81800000 10000 >;<br>
> >> xlnx,num-intr-inputs = <7>;<br>
> >> } ;<br>
> >> } ;<br>
> >> ppc405_0_dplb1: plb@1 {<br>
> >> #address-cells = <1>;<br>
> >> #size-cells = <1>;<br>
> >> compatible = "xlnx,plb-v46-1.02.a";<br>
> >> ranges ;<br>
> >> } ;<br>
> >> } ;<br>
> >><br>
> >><br>
> >><br>
> >> -----Original Message-----<br>
> >> From: Magnus Hjorth [mailto:<a href="mailto:mh@omnisys.se">mh@omnisys.se</a>]<br>
> >> Sent: Saturday, March 29, 2008 6:54 AM<br>
> >> To: git<br>
> >> Cc: <a href="mailto:linuxppc-embedded@ozlabs.org">linuxppc-embedded@ozlabs.org</a><br>
> >> Subject: Xilinx LLTEMAC driver issues<br>
> >><br>
> >> Hi,<br>
> >><br>
> >> I'm having some networking troubles with the Xilinx LLTEMAC driver from the<br>
> >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,<br>
> >> xps_ll_temac v1.00.b<br>
> >><br>
> >> The weird thing is, that it sort of half works. It successfully makes a DHCP<br>
> >> request and gets its IP address. I tried setting up a tftpd server, and I can<br>
> >> see UDP requests coming in but the response doesn't seem to come out. I also<br>
> >> tried running a TCP server on the board, and it can see and accept incoming<br>
> >> connections but after that no data seems to get through. I can ping out and<br>
> >> get around 40% packet loss.<br>
> >><br>
> >> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma<br>
> >> interrupts. No eth0 interrupts but that seems to be OK judging by the driver<br>
> >> source comments. Ifconfig shows no collistions, no dropped packets, no<br>
> errors,<br>
> >> so the system seems to think that everything is OK.<br>
> >><br>
> >> Clues anyone? I'm starting to run out of ideas...<br>
> >><br>
> >> Best regards,<br>
> >> Magnus<br>
> >><br>
> >><br>
> >> --<br>
> >><br>
> >> Magnus Hjorth, M.Sc.<br>
> >> Omnisys Instruments AB<br>
> >> Gruvgatan 8<br>
> >> SE-421 30 Västra Frölunda, SWEDEN<br>
> >> Phone: +46 31 734 34 09<br>
> >> Fax: +46 31 734 34 29<br>
> >> <a href="http://www.omnisys.se" target="_blank">http://www.omnisys.se</a><br>
> >><br>
> ><br>
> > _______________________________________________<br>
> > Linuxppc-embedded mailing list<br>
> > <a href="mailto:Linuxppc-embedded@ozlabs.org">Linuxppc-embedded@ozlabs.org</a><br>
> > <a href="https://ozlabs.org/mailman/listinfo/linuxppc-embedded" target="_blank">https://ozlabs.org/mailman/listinfo/linuxppc-embedded</a><br>
_______________________________________________<br>
Linuxppc-embedded mailing list<br>
<a href="mailto:Linuxppc-embedded@ozlabs.org">Linuxppc-embedded@ozlabs.org</a><br>
<a href="https://ozlabs.org/mailman/listinfo/linuxppc-embedded" target="_blank">https://ozlabs.org/mailman/listinfo/linuxppc-embedded</a></div></div></blockquote></div><br><br clear="all"><br>-- <br>Johann Baudy<br><a href="mailto:johaahn@gmail.com">johaahn@gmail.com</a>