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llandre,<br><br>Our tests show that V4 FX 12 is really a small device. The FPGA was completely full with these set of modules:<br><br>1- CPU core and related circuits, 2- PLB TEMAC , 3- DDR SDRAM Controller , 4- PLB BRAM IF , 5- Bridges , 6- OPB UART and 7- OPB EMC controller (Used for interfacing to flash chips )<br><br>The synthesis tool we used during our tests was : XST<br>it seems that there are some solutions to have a more optimized implementation on FX-12, personally i visited one of the members here who claimed that he has two PLB TEMACs enabled on one FX-12 FPGA. I believe that this is not possible. may be if one use better synthesis tools such as Synplify he may get slightly better results.<br><br>any how, in my idea FX-12 is not suitable for serious projects, it is suitable only for beginning phases of a project and the research phase. <br>We are now focusing on ML410, a great board by Xiling, featuring on FX-60 FPGA while keeps costs low.<br><br>any questions are welcom,<br>thanks,<br>Mohammad.<br><br><br>> Date: Wed, 13 Feb 2008 10:32:58 +0100<br>> From: r&d2@dave-tech.it<br>> To: mamsadegh@hotmail.com<br>> CC: linuxppc-embedded@ozlabs.org<br>> Subject: V4 FX12 and PLB TEMAC: no space for user logic?<br>> <br>> Hi Mohammad,<br>> <br>> I've just had a look at the messages you generously posted in the ml <br>> about your experience with linux on V4 FX12 FPGA.<br>> I'd like to ask your opinion about FX12 practical usability in this <br>> context (gigabit PLB TEMAC/linux).<br>> In this message<br>> <br>> http://article.gmane.org/gmane.linux.ports.ppc.embedded/16816<br>> <br>> you say the device is completely full. If I understand correctly your <br>> system provides just the devices required to run the bandwidth test so <br>> it seems there is no room for user logic (I think you did not even add <br>> the memory controller required to access the NOR Flash containing <br>> bootloader, kernel image and root fs that is clearly mandatory for <br>> standalone product). Is that true? If it is, this limits a lot the <br>> flexibility of this architecture in this configuration. What do you think?<br>> <br>> <br>> <br>> Regards,<br>> llandre<br>> <br>> DAVE Electronics System House - R&D Department<br>> web: http://www.dave.eu<br>> email: r&d2@dave-tech.it<br><br /><hr /> <a href='' target='_new'></a></body>
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