<div>Hi All,</div>
<div> </div>
<div>I m using Linux 2.6.23-rc2 from Grant's git with gcc 4.1.0 on ML-403. When I load the zImage from the XMD, I only get the messages printed from the arch/ppc/boot and soon after the kernel is decompressed the console appears frozen. So I assume the console is ok with image loader but on linux kernel, it doesnt seem working. I edited the code in arch/ppc/boot/simple so as to forcefully refer the right embed_config() function.
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<div> </div>
<div>Following is the console logs,</div>
<div>loaded at: 00400000 004D71A0<br>board data at: 004D5124 004D51A0<br>relocated to: 00404048 004040C4<br>zimage at: 00404F11 004D4DFC<br>avail ram: 004D8000 02000000<br>Linux/PPC load: console=ttyS0,9600<br>
Uncompressing Linux...done.<br>Now booting the kernel<br>com_port is 40401003<br>id mach(): done<br>MMU:enter<br>MMU:hw init<br>MMU:mapin<br>MMU:setio<br>MMU:exit</div>
<div> </div>
<div>When I dumped the __log_buffer, I only find the linux_banner being displayed, the others remain zero. Periodically I stopped the ppc to find the PC using XMD. Eachtime I stopped it was different either with address 0xCxxx_xxxx or 0x0xxx_xxxx. So I suspect this could be a console problem as kernel appears running.
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<div>It would be helpful if someone could let me know, whether anything more needs to be done to bring the console. In xparameters_ml403.h the PLB speed is 100000000 and I havent edited any other file. Also, I have configured the command line parameters to kernel as CONFIG_CMDLINE="console=ttyS0,9600".
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<div>Whether there are any conflicts between the compiler being used and linux version despite the changes to correctly refer the embed_config(). Also, please let me know whether printk keeps dumping on __log_buffer even after the console is initialized and are there anyway to keep printk dumping to __log_buffer irrespective of the console being initialzed or not.
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<div>Any suggestions and ideas would be very helpful.</div>
<div> </div>
<div>Thanks and Regards,</div>
<div>Ram</div>
<div> </div>
<div> </div>
<div>PS: Attached is config file and below is xparameters file</div>
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<div>xparameters_ml403.h</div>
<div>------------------------------------------------------</div>
<div>/* Definitions for driver UARTNS550 */<br>#define XPAR_XUARTNS550_NUM_INSTANCES 1<br>#define XPAR_XUARTNS550_CLOCK_HZ 100000000</div>
<div>/* Definitions for peripheral RS232_UART */<br>#define XPAR_RS232_UART_BASEADDR 0x40400000<br>#define XPAR_RS232_UART_HIGHADDR 0x4040FFFF<br>#define XPAR_RS232_UART_DEVICE_ID 0</div>
<div><br>/******************************************************************/</div>
<div>/* Definitions for driver IIC */<br>#define XPAR_XIIC_NUM_INSTANCES 1</div>
<div>/* Definitions for peripheral IIC_EEPROM */<br>#define XPAR_IIC_EEPROM_BASEADDR 0x40800000<br>#define XPAR_IIC_EEPROM_HIGHADDR 0x4080FFFF<br>#define XPAR_IIC_EEPROM_DEVICE_ID 0<br>#define XPAR_IIC_EEPROM_TEN_BIT_ADR 0
<br>#define XPAR_IIC_EEPROM_GPO_WIDTH 1</div>
<div><br>/******************************************************************/</div>
<div>#define XPAR_XSYSACE_MEM_WIDTH 16<br>/* Definitions for driver SYSACE */<br>#define XPAR_XSYSACE_NUM_INSTANCES 1</div>
<div>/* Definitions for peripheral SYSACE_COMPACTFLASH */<br>#define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000<br>#define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF<br>#define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0<br>
#define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16</div>
<div><br>/******************************************************************/</div>
<div><br>/* Definitions for peripheral SRAM_256KX32 */<br>#define XPAR_SRAM_256KX32_NUM_BANKS_MEM 1</div>
<div><br>/******************************************************************/</div>
<div>/* Definitions for peripheral SRAM_256KX32 */<br>#define XPAR_SRAM_256KX32_MEM0_BASEADDR 0x40500000<br>#define XPAR_SRAM_256KX32_MEM0_HIGHADDR 0x405FFFFF</div>
<div>/******************************************************************/</div>
<div>#define XPAR_INTC_MAX_NUM_INTR_INPUTS 4<br>#define XPAR_XINTC_HAS_IPR 1<br>#define XPAR_XINTC_USE_DCR 0<br>/* Definitions for driver INTC */<br>#define XPAR_XINTC_NUM_INSTANCES 1</div>
<div>/* Definitions for peripheral OPB_INTC_0 */<br>#define XPAR_OPB_INTC_0_BASEADDR 0x41200000<br>#define XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF<br>#define XPAR_OPB_INTC_0_DEVICE_ID 0<br>#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
</div>
<div><br>/******************************************************************/</div>
<div>#define XPAR_INTC_SINGLE_BASEADDR 0x41200000<br>#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF<br>#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID<br>#define XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK 0X000001<br>
#define XPAR_OPB_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR 0<br>#define XPAR_SYSACE_COMPACTFLASH_SYSACE_IRQ_MASK 0X000002<br>#define XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR 1<br>#define XPAR_IIC_EEPROM_IP2INTC_IRPT_MASK 0X000004
<br>#define XPAR_OPB_INTC_0_IIC_EEPROM_IP2INTC_IRPT_INTR 2<br>#define XPAR_RS232_UART_IP2INTC_IRPT_MASK 0X000008<br>#define XPAR_OPB_INTC_0_RS232_UART_IP2INTC_IRPT_INTR 3</div>
<div>/******************************************************************/</div>
<div>/* Definitions for driver DDR */<br>#define XPAR_XDDR_NUM_INSTANCES 1</div>
<div>/* Definitions for peripheral DDR_SDRAM_64MX32 */<br>#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF<br>#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000<br>#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0<br>#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
</div>
<div><br>/******************************************************************/</div>
<div>/* Definitions for peripheral DDR_SDRAM_64MX32 */<br>#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000<br>#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF</div>
<div>/******************************************************************/</div>
<div>/* Definitions for driver EMAC */<br>#define XPAR_XEMAC_NUM_INSTANCES 1</div>
<div>/* Definitions for peripheral ETHERNET_MAC */<br>#define XPAR_ETHERNET_MAC_BASEADDR 0x80400000<br>#define XPAR_ETHERNET_MAC_HIGHADDR 0x8040FFFF<br>#define XPAR_ETHERNET_MAC_DEVICE_ID 0<br>#define XPAR_ETHERNET_MAC_ERR_COUNT_EXIST 1
<br>#define XPAR_ETHERNET_MAC_DMA_PRESENT 1<br>#define XPAR_ETHERNET_MAC_MII_EXIST 1<br>/* Edited by Ramkumar. Dont know whether this will be working.<br> */<br>#define XPAR_ETHERNET_MAC_CAM_EXIST 0<br>#define XPAR_ETHERNET_MAC_JUMBO_EXIST 0
<br>#define XPAR_ETHERNET_MAC_TX_DRE_TYPE 0<br>#define XPAR_ETHERNET_MAC_RX_DRE_TYPE 0<br>#define XPAR_ETHERNET_MAC_TX_INCLUDE_CSUM 0<br>#define XPAR_ETHERNET_MAC_RX_INCLUDE_CSUM 0</div>
<div><br>/******************************************************************/</div>
<div><br>/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */<br>#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff0000<br>#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff</div>
<div><br>/******************************************************************/</div>
<div>#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000</div>
<div>/******************************************************************/</div>
<div>#define XPAR_CPU_ID 0<br>#define XPAR_PPC405_VIRTEX4_ID 0<br>#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 100000000<br>#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100<br>#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x0000010F
<br>#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1<br>#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1<br>#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0<br>#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1<br>#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011<br>#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
<br>#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000<br>#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000<br>#define XPAR_PPC405_VIRTEX4_HW_VER "1.01.a"</div>
<div>/******************************************************************/</div>
<div><br>/******************************************************************/</div>
<div>/* Linux Redefines */</div>
<div>/******************************************************************/</div>
<div>#define XPAR_UARTNS550_0_BASEADDR (XPAR_RS232_UART_BASEADDR+0x1000)<br>#define XPAR_UARTNS550_0_HIGHADDR XPAR_RS232_UART_HIGHADDR<br>#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ<br>#define XPAR_UARTNS550_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
</div>
<div>/******************************************************************/</div>
<div>#define XPAR_IIC_0_BASEADDR XPAR_IIC_EEPROM_BASEADDR<br>#define XPAR_IIC_0_HIGHADDR XPAR_IIC_EEPROM_HIGHADDR<br>#define XPAR_IIC_0_TEN_BIT_ADR XPAR_IIC_EEPROM_TEN_BIT_ADR<br>#define XPAR_IIC_0_DEVICE_ID XPAR_IIC_EEPROM_DEVICE_ID
</div>
<div>/******************************************************************/</div>
<div>#define XPAR_SYSACE_0_BASEADDR XPAR_SYSACE_COMPACTFLASH_BASEADDR<br>#define XPAR_SYSACE_0_HIGHADDR XPAR_SYSACE_COMPACTFLASH_HIGHADDR<br>#define XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMPACTFLASH_DEVICE_ID</div>
<div>/******************************************************************/</div>
<div>#define XPAR_EMAC_0_BASEADDR XPAR_ETHERNET_MAC_BASEADDR<br>#define XPAR_EMAC_0_HIGHADDR XPAR_ETHERNET_MAC_HIGHADDR<br>#define XPAR_EMAC_0_DMA_PRESENT XPAR_ETHERNET_MAC_DMA_PRESENT<br>#define XPAR_EMAC_0_MII_EXIST XPAR_ETHERNET_MAC_MII_EXIST
<br>#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_ETHERNET_MAC_ERR_COUNT_EXIST<br>#define XPAR_EMAC_0_CAM_EXIST XPAR_ETHERNET_MAC_CAM_EXIST<br>#define XPAR_EMAC_0_JUMBO_EXIST XPAR_ETHERNET_MAC_JUMBO_EXIST<br>#define XPAR_EMAC_0_TX_DRE_TYPE XPAR_ETHERNET_MAC_TX_DRE_TYPE
<br>#define XPAR_EMAC_0_RX_DRE_TYPE XPAR_ETHERNET_MAC_RX_DRE_TYPE<br>#define XPAR_EMAC_0_TX_INCLUDE_CSUM XPAR_ETHERNET_MAC_TX_INCLUDE_CSUM<br>#define XPAR_EMAC_0_RX_INCLUDE_CSUM XPAR_ETHERNET_MAC_RX_INCLUDE_CSUM<br>#define XPAR_EMAC_0_DEVICE_ID XPAR_ETHERNET_MAC_DEVICE_ID
</div>
<div>/******************************************************************/</div>
<div>#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR<br>#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR<br>#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR<br>#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
</div>
<div>/******************************************************************/</div>
<div>#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR<br>#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR<br>#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_IIC_EEPROM_IP2INTC_IRPT_INTR
<br>#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_RS232_UART_IP2INTC_IRPT_INTR</div>
<div>/******************************************************************/</div>
<div>#define XPAR_PLB_CLOCK_FREQ_HZ 100000000<br>#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ<br>#define XPAR_DDR_0_SIZE 33554432</div>
<div>/******************************************************************/</div>
<div>#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400<br>#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF<br>#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0</div>
<div>/******************************************************************/</div>
<div>#define XPAR_PCI_0_CLOCK_FREQ_HZ 0</div>
<div>/******************************************************************/</div>
<div>#define XPAR_XPS2_NUM_INSTANCES 2<br>#define XPAR_PS2_0_DEVICE_ID 50<br>#define XPAR_PS2_0_BASEADDR 0xA9000000<br>#define XPAR_PS2_0_HIGHADDR 0xA900003F<br>#define XPAR_INTC_0_PS2_0_VEC_ID 27
<br>#define XPAR_PS2_1_DEVICE_ID 51<br>#define XPAR_PS2_1_BASEADDR 0xA9001000<br>#define XPAR_INTC_0_PS2_1_VEC_ID 26</div>
<div>/******************************************************************/<br></div>
<div> </div>