<div>Here is the PC value before the rfi:</div>
<div> </div>
<div>cds8458>halt</div>
<div> Target CPU: : MPC85xx (e500v2 rev.1)</div>
<div> Target state : halted</div>
<div> Debug entry cause : instruction breakpoint</div>
<div> Current PC : 0x0000015c</div>
<div> Current CR : 0x24024022</div>
<div> Current MSR : 0x00012100</div>
<div> Current LR :0x00000148</div>
<div> Current CCSRBAR :0x0_e000000</div>
<div> </div>
<div>After the rfi:</div>
<div> </div>
<div>#step timeout defected</div>
<div>
<div>cds8458>halt</div>
<div> Target CPU: : MPC85xx (e500v2 rev.1)</div>
<div> Target state : halted</div>
<div> Debug entry cause : COP halt</div>
<div> Current PC : 0xfff81300</div>
<div> Current CR : 0x24024022</div>
<div> Current MSR : 0x00001000</div>
<div> Current LR :0x00000148</div>
<div> Current CCSRBAR :0x0_e000000</div></div>
<div><br><br> </div>
<div><span class="gmail_quote">On 8/15/07, <b class="gmail_sendername">Becky Bruce</b> <<a href="mailto:becky.bruce@freescale.com">becky.bruce@freescale.com</a>> wrote:</span>
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid"><br>On Aug 15, 2007, at 8:59 AM, mike zheng wrote:<br><br>> I use BDI to debug these two instructions. And here are the output
<br>> of BDI just before the "rfi". The content of R6, R7 is different<br>> from SRR0(SPR26) and SRR1(SPR27).<br><br>I see you have not printed the pc/nia once you stop. Are you sure<br>you're stopped where you think? Please check this.
<br><br>-B<br><br>><br>> cds8548>res run<br>><br>> - TARGET: processing user reset request<br>><br>> - BDI asserts HRESET<br>><br>> - Reset JTAG controller passed<br>><br>> - JTAG exists check passed
<br>><br>> - IDCODE is 0x0003901D<br>><br>> - SVR is 0x80390011<br>><br>> - PVR is 0x80210010<br>><br>> - CCSRBAR is 0x0_ff700000<br>><br>> - BDI removes HRESET<br>><br>> - TARGET: Target PVR is 0x80210010
<br>><br>> - TARGET: resetting target passed<br>><br>> cds8548>halt<br>><br>> Target CPU : MPC85xx (e500v2 rev.1)<br>><br>> Target state : halted<br>><br>> Debug entry cause : COP halt<br>
><br>> Current PC : 0xfff82560<br>><br>> Current CR : 0x88000042<br>><br>> Current MSR : 0x00021200<br>><br>> Current LR : 0xfff8aa4c<br>><br>> Current CCSRBAR : 0x0_e0000000<br>><br>> cds8548>ci
<br>><br>> cds8548>bi 0x0000015c<br>><br>> Breakpoint identification is 0<br>><br>> cds8548>go<br>><br>> - TARGET: stopped<br>><br>> cds8548>rd<br>><br>> GPR00: 00000000 0ffabd20 00000200 00000008
<br>><br>> GPR04: 00000000 00000001 00000020 00000160<br>><br>> GPR08: 1f8b0808 00000148 0ffabace 0ffe08b0<br>><br>> GPR12: 00000006 764deddb 10000300 007fff00<br>><br>> GPR16: 00000001 ffffffff 007fff25 0ffff9d8
<br>><br>> GPR20: 007ffeb0 00000000 0fffaa3c 0ffae490<br>><br>> GPR24: 00000000 00000003 02000040 007fff25<br>><br>> GPR28: 007fff00 0ffab3b8 0fcd6000 007ffeb0<br>><br>> CR : 24024022 MSR: 00021200
<br>><br>> cds8548>rdspr 26<br>><br>> SPR 26 : 0xfff81300 - 519424<br>><br>> cds8548>rdspr 27<br>><br>> SPR 27 : 0x00001000 4096<br>><br>> cds8548><br>><br>><br>><br>><br>
><br>><br>> On 8/14/07, Andy Fleming <<a href="mailto:afleming@freescale.com">afleming@freescale.com</a>> wrote:<br>> On Aug 14, 2007, at 15:21, mike zheng wrote:<br>><br>> ><br>> > Hi All,
<br>> ><br>> > I am trying to bring up MPC8548 CDS board on 2.4 kernel. I have<br>> > problem in the head_e500.S. The "mtspr SRR0, r7; mtspr SRR1 r6"<br>> > does not work for me. The content of R7 and R6 are not moved to
<br>> > SRR0 and SRR1. I am using the tool-chain from Freescale for 2.6<br>> > kernel.<br>> ><br>> > Any idea on this issue?<br>><br>> Just to check...how do you know it doesn't work?<br>
><br>> Andy<br>><br>> _______________________________________________<br>> Linuxppc-embedded mailing list<br>> <a href="mailto:Linuxppc-embedded@ozlabs.org">Linuxppc-embedded@ozlabs.org</a><br>> <a href="https://ozlabs.org/mailman/listinfo/linuxppc-embedded">
https://ozlabs.org/mailman/listinfo/linuxppc-embedded</a><br><br></blockquote></div><br>