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Daniel Jacobowitz wrote:
<blockquote cite="mid20070718183143.GA25324@caradoc.them.org"
type="cite">
<pre wrap="">On Wed, Jul 18, 2007 at 12:59:42PM -0500, Bill Gatliff wrote:
</pre>
<blockquote type="cite">
<pre wrap="">Now, I'm a little rusty on PPC asm (I've been doing a lot of ARM
lately), but it looks to me like the kernel is setting bit 0 in CR0
(oris r10, r10, 0x1000) a.k.a LT, but the user side is looking at CR0
(bnslr+) bit 3 a.k.a. SO. Or maybe the other way around, I'm not sure
after reading Sections 1.2 and 2.1 of the Programming Environments manual.
</pre>
</blockquote>
<pre wrap=""><!---->
It's not checking for restart here - userspace isn't supposed to have to.
It's probably checking for error. Check for the bit of kernel code
that's supposed to back you up two instructions.
</pre>
</blockquote>
<br>
I don't see it in this kernel. What I see is this after the call to
the syscall handler:<br>
<br>
<tt> li r10,-_LAST_ERRNO<br>
cmpl 0,r3,r10<br>
blt 30f<br>
neg r3,r3<br>
cmpi 0,r3,ERESTARTNOHAND<br>
bne 22f<br>
li r3,EINTR<br>
22: lwz r10,_CCR(r1) /* Set SO bit in CR */<br>
oris r10,r10,0x1000<br>
stw r10,_CCR(r1)<br>
30: stw r3,GPR3(r1) /* Update return value */<br>
b ret_from_except<br>
66: li r3,ENOSYS<br>
b 22b<br>
</tt><br>
<br>
?<br>
<br>
<pre class="moz-signature" cols="80">--
Bill Gatliff
<a class="moz-txt-link-abbreviated" href="mailto:bgat@billgatliff.com">bgat@billgatliff.com</a>
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