<div>Hi,</div> <div> </div> <div>We have a custom 8248 card that we are testing. </div> <div>The core is running at 400MHz and the system bus is 80Mhz (measured and verified), 32 bit wide memory interface.</div> <div>There is nothing connected to the CPM except 1 RS232 port which is not used in our test loop.</div> <div> </div> <div>We are running a small test C loop (with approx. 60 assembly language instructions) at the end of u-boot as in the Hello World example. The loop runs fine but upon closer analisis I found that each loop takes 6uS. This averages out to 100nS/instruction = 10MIPS = sad performance. I would have expected at least 100MIPS or more.</div> <div> </div> <div>I've checked the HID0 SPR register to verify that the instruction cache is enabled.</div> <div> </div> <div>I've also stepped thru the code to verify that the code stays within the loop (no async branches or irqs). Looking at the adr and data lines with an
analyzer the loop appears to do the correct amount of I/O to SDRAM but the amount of time of between SDRAM accesses seem longer than I would expect if caching, pipelining, snooping, etc are enabled.</div> <div> </div> <div>Any ideas on what could be slowing the CPU down are greatly appreciated.</div> <div> </div> <div>Paul</div><p> 
<hr size=1>Don't pick lemons.<br>
See all the <a href="http://autos.yahoo.com/new_cars.html;_ylc=X3oDMTE0OGRsc3F2BF9TAzk3MTA3MDc2BHNlYwNtYWlsdGFncwRzbGsDbmV3Y2Fycw--">new 2007 cars</a> at <a href="http://autos.yahoo.com/new_cars.html;_ylc=X3oDMTE0OGRsc3F2BF9TAzk3MTA3MDc2BHNlYwNtYWlsdGFncwRzbGsDbmV3Y2Fycw--">Yahoo! Autos.</a>