Hi,<br> <br> We got it to load into DDR ram, based on a comment you made earlier about how the system ace works.<br> <br> In our genace.opt file (the one we made ourselves), an engineer had put<br>-debugdevice devicenr 1 cpunr 2
<br><br> It turns out that the last "debugdevice" being used is the one that the system ace chip uses to gain control of to download the elf file into ram. We had picked the cpu that was not tied to the plb bus, so it could not write to ram. The system ace did not care and did not error out.
<br><br> Once we set it to <br>-debugdevice devicenr 1 cpunr 1<br><br> then it loaded into ram and tried. to execute. We are now having DDR ram problems, we are trying to solve those problems.<br><br>thanks again for your help!
<br><br>wade<br><br><br><div><span class="gmail_quote">On 1/23/07, <b class="gmail_sendername"><a href="mailto:linux-ppc@eurotel.it">linux-ppc@eurotel.it</a></b> <<a href="mailto:linux-ppc@eurotel.it">linux-ppc@eurotel.it
</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<br><font face="sans-serif" size="2">Hi Wade,</font>
<br><font face="sans-serif" size="2">we made our board from scratch, there
are two FPGA, one FX12 and one SX35, loaded with system ace,Montavista
Linux and everything is ok.</font>
<br><font face="sans-serif" size="2">Is the JTAG chain in the correct sequence?</font>
<br><font face="sans-serif" size="2">are there in your board only one fpga
or there is a chain with two fpga? if yes the Xilinx documentation with
genace.tcl fails to concatenate two fpga files.</font>
<br><font face="sans-serif" size="2">also verify the tools errors manually
executing the genace.tcl commands; they are not so difficult to understand.</font>
<br><font face="sans-serif" size="2">also verify that bootlloop code is loaded
into the fabric ram.</font>
<br><font face="sans-serif" size="2">keep in mind that your memory is to
be loaded via JTAG command, so if FPGA load correctly and DDR is working,
then there is no reason to have DDR load failure.</font>
<br><font face="sans-serif" size="2">regards</font>
<br>
<br>
<br>
<table width="100%">
<tbody><tr valign="top">
<td width="40%"><font face="sans-serif" size="1"><b>"Wade Maxfield"
<<a href="mailto:wmaxfield@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">wmaxfield@gmail.com</a>></b> </font>
<br><font face="sans-serif" size="1">Sent by: linuxppc-embedded-bounces+linux-ppc=<a href="mailto:eurotel.it@ozlabs.org" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">eurotel.it@ozlabs.org</a></font>
<p><font face="sans-serif" size="1">05/01/2007 17.23</font>
</p></td><td width="59%">
<table width="100%">
<tbody><tr valign="top">
<td>
<div align="right"><font face="sans-serif" size="1">To</font></div>
</td><td><font face="sans-serif" size="1"><a href="mailto:christophe.alayrac@cresitt.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">christophe.alayrac@cresitt.com</a></font>
</td></tr><tr valign="top">
<td>
<div align="right"><font face="sans-serif" size="1">cc</font></div>
</td><td><font face="sans-serif" size="1">ppc <<a href="mailto:linuxppc-embedded@ozlabs.org" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">linuxppc-embedded@ozlabs.org</a>></font>
</td></tr><tr valign="top">
<td>
<div align="right"><font face="sans-serif" size="1">Subject</font></div>
</td><td><font face="sans-serif" size="1">Re: System Ace booting (or not) question</font></td></tr></tbody></table>
<br>
<table>
<tbody><tr valign="top">
<td>
<br></td><td><br></td></tr></tbody></table>
<br></td></tr></tbody></table><div><span class="e" id="q_1104e5cf8d66e168_1">
<br>
<br>
<br><font size="3">Hi Alayrac,<br>
<br>
Thank you for your reply.<br>
<br>
No, there is no bus error.<br>
<br>
The memory map of our design matches the ML403 as regards the DDR
ram. We are just trying to get the code into external DDR Ram.<br>
<br>
The code start address is specified in the elf file, and lists correctly
on the screen as the genace script executes.<br>
<br>
The code in zImage.elf is compiled to the DDR space, and so should
load there. The genace script prints out the code will load there
when it runs and places <br>
the .elf file into the system. The system.ace file is 10 megabytes
after the zImage.elf code is put into it. when doing only the internal
block ram load, the system.ace<br>
file is only 2.8 megabytes in size.<br>
<br>
<br>
thanks again,<br>
wade<br>
<br>
<br>
<br>
</font>
<br><font size="3">On 1/5/07, <b>alayrac christophe</b> <</font><a href="mailto:christophe.alayrac@cresitt.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)"><font color="blue" size="3"><u>christophe.alayrac@cresitt.com
</u></font></a><font size="3">
> wrote:</font>
<br><font size="3">High Wade,<br>
<br>
Does systemace comes out with a bus error? (Red led on ML403 board)? <br>
<br>
If yes may be its because the memory map of your design did not fit with<br>
ML403 ones and that SystemaAce try to load kernel image in a non ram<br>
place.<br>
<br>
you may have to specify the code start address to the genace.tcl script<br>
to generate properly the ace file. (it should be something like<br>
start_address 0xYOURADDR in the opt file)<br>
<br>
Have you tried to download the kernel image through JTAG?<br>
<br>
You can also try to compile a standalone code in DDR space (not BRAM as
<br>
describe in your email) an try to make an ace file with it.<br>
<br>
regards<br>
<br>
Chris<br>
<br>
Le vendredi 05 janvier 2007 à 09:20 -0600, Wade Maxfield a écrit :<br>
><br>
> I'm very new to System Ace, and this is probably a stupid question.
<br>
><br>
> We were able, with the Monta Vista Linux to get a system.ace
with a<br>
> zImage.elf linux file to boot on an ml403 board. The system
ace chip<br>
> seemed to copy the zImage.elf into DDR ram, and the system booted.
No <br>
> block ram used.<br>
><br>
> We created a board with an xf60 and a system ace chip
on it and<br>
> created a system.ace file. The xilinx loads, but the zImage.elf
does<br>
> not copy into ddr ram. We ran the testfatfs code and read from
and <br>
> wrote to the compact flash on the system ace chip, verifying the files<br>
> through a compact flash adaptor on a pc.<br>
><br>
> We created a memory test using the ppc and were able
(after some<br>
> wiring changes and other headaches) to prove the ddr ram works. There
<br>
> is enough of it to support linux (64 meg), and testing all 64 million<br>
> locations with various fixed and incrementing patterns proves it<br>
> works.<br>
><br>
> However, we could not get the external ram to load up
with the <br>
> linux zImage.elf file. When this failed, we created a system.ace file<br>
> with two elf's in it, one for linux, one for a memory read/write<br>
> tester in block ram.<br>
><br>
> It appears the system ace chip loads the info into block ram
just <br>
> fine, and our memory test executes. However, our ddr ram has
nothing<br>
> in it. We reversed the order of the elf files, and that still
did not<br>
> help.<br>
><br>
> Do we need a helper CPLD on this board to accomplish what the
ML403 <br>
> accomplishes? Or do we need to do a boot loader in code? If
we need<br>
> to do a boot loader, how come the Monta Vista linux doesn't need one<br>
> on the ml403 board? I've been googling and scouring the Xilinx
site, <br>
> but I've achieved nothing but a few less hairs on my head.<br>
><br>
> I've already asked Monta Vista this question, and they quoted<br>
> verbatim the page from the xilinx manual, which is a generic answer
to <br>
> the specific question. Even if the xilinx manual is the answer,
we<br>
> aren't seeing the results the manual implies we will see.<br>
><br>
> Can someone give me a clue?<br>
><br>
> thanks,<br>
> wade <br>
><br>
> _______________________________________________<br>
> Linuxppc-embedded mailing list<br>
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