Hi Alayrac,<br><br> Thank you for your reply.<br><br> No, there is no bus error.<br><br> The memory map of our design matches the ML403 as regards the DDR ram. We are just trying to get the code into external DDR Ram.<br>
<br> The code start address is specified in the elf file, and lists correctly on the screen as the genace script executes.<br><br> The code in zImage.elf is compiled to the DDR space, and so should load there. The genace script prints out the code will load there when it runs and places
<br>the .elf file into the system. The system.ace file is 10 megabytes after the zImage.elf code is put into it. when doing only the internal block ram load, the system.ace<br>file is only 2.8 megabytes in size.<br><br>
<br>thanks again,<br>wade<br><br><br><br><br><div><span class="gmail_quote">On 1/5/07, <b class="gmail_sendername">alayrac christophe</b> <<a href="mailto:christophe.alayrac@cresitt.com">christophe.alayrac@cresitt.com</a>
> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">High Wade,<br><br>Does systemace comes out with a bus error? (Red led on ML403 board)?
<br><br>If yes may be its because the memory map of your design did not fit with<br>ML403 ones and that SystemaAce try to load kernel image in a non ram<br>place.<br><br>you may have to specify the code start address to the
genace.tcl script<br>to generate properly the ace file. (it should be something like<br>start_address 0xYOURADDR in the opt file)<br><br>Have you tried to download the kernel image through JTAG?<br><br>You can also try to compile a standalone code in DDR space (not BRAM as
<br>describe in your email) an try to make an ace file with it.<br><br>regards<br><br>Chris<br><br>Le vendredi 05 janvier 2007 à 09:20 -0600, Wade Maxfield a écrit :<br>><br>> I'm very new to System Ace, and this is probably a stupid question.
<br>><br>> We were able, with the Monta Vista Linux to get a system.ace with a<br>> zImage.elf linux file to boot on an ml403 board. The system ace chip<br>> seemed to copy the zImage.elf into DDR ram, and the system booted. No
<br>> block ram used.<br>><br>> We created a board with an xf60 and a system ace chip on it and<br>> created a system.ace file. The xilinx loads, but the zImage.elf does<br>> not copy into ddr ram. We ran the testfatfs code and read from and
<br>> wrote to the compact flash on the system ace chip, verifying the files<br>> through a compact flash adaptor on a pc.<br>><br>> We created a memory test using the ppc and were able (after some<br>> wiring changes and other headaches) to prove the ddr ram works. There
<br>> is enough of it to support linux (64 meg), and testing all 64 million<br>> locations with various fixed and incrementing patterns proves it<br>> works.<br>><br>> However, we could not get the external ram to load up with the
<br>> linux zImage.elf file. When this failed, we created a system.ace file<br>> with two elf's in it, one for linux, one for a memory read/write<br>> tester in block ram.<br>><br>> It appears the system ace chip loads the info into block ram just
<br>> fine, and our memory test executes. However, our ddr ram has nothing<br>> in it. We reversed the order of the elf files, and that still did not<br>> help.<br>><br>> Do we need a helper CPLD on this board to accomplish what the ML403
<br>> accomplishes? Or do we need to do a boot loader in code? If we need<br>> to do a boot loader, how come the Monta Vista linux doesn't need one<br>> on the ml403 board? I've been googling and scouring the Xilinx site,
<br>> but I've achieved nothing but a few less hairs on my head.<br>><br>> I've already asked Monta Vista this question, and they quoted<br>> verbatim the page from the xilinx manual, which is a generic answer to
<br>> the specific question. Even if the xilinx manual is the answer, we<br>> aren't seeing the results the manual implies we will see.<br>><br>> Can someone give me a clue?<br>><br>> thanks,<br>> wade
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