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<DIV><FONT face=Arial size=2>MPC83xx cpu has two PCI buses. This patch adds
support for them.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>After system boot. The code initializes PCI
inbound/outbound<BR>windows, allocate and register PCI memory/io space. Be
aware<BR>that this patch depand on the firmware.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Signed-off-by: Tony Li <<A
href="mailto:tony.li@freescale.com">tony.li@freescale.com</A>></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>---<BR>author Tony Li <<A
href="mailto:tony.li@freescale.com">tony.li@freescale.com</A>> Tue, 30 Aug
2005<BR>committer Tony Li <<A
href="mailto:tony.li@freescale.com">tony.li@freescale.com</A>> Tue, 30 Aug
2005</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>diff -urN -X dontdiff
linux-2.6.13-rc6/arch/ppc/Kconfig linux-2.6.13-rc6-pci/arch/ppc/Kconfig<BR>---
linux-2.6.13-rc6/arch/ppc/Kconfig 2005-08-09 18:00:47.000000000
+0800<BR>+++ linux-2.6.13-rc6-pci/arch/ppc/Kconfig 2005-08-19
18:17:27.000000000 +0800<BR>@@ -712,6 +712,11 @@<BR> bool "Freescale
MPC834x SYS"<BR> help<BR> This option enables
support for the MPC 834x SYS evaluation board.<BR>+ Be aware that
PCI buses can only function when SYS board is plugged on<BR>+ PIB
(Platform IO Board) board from Freescale which provide 3 PCI
slots.<BR>+ Just like PC,the board level initalization is
bootloader`s responsiblilty.<BR>+ The PCI deponds on bootloader
configurate board corretly. Refer to Freescale<BR>+ to get more
information about this. <BR> <BR> endchoice<BR> <BR>@@ -1191,6
+1196,10 @@<BR> bool<BR> default PCI<BR> <BR>+config
MPC834x_PCI2<BR>+ bool<BR>+ default y if PCI &&
MPC834x_SYS<BR>+<BR> config PCI_QSPAN<BR> bool "QSpan
PCI"<BR> depends on !4xx && !CPM2 && 8xx<BR>diff -urN
-X dontdiff linux-2.6.13-rc6/arch/ppc/platforms/83xx/mpc834x_sys.c
linux-2.6.13-rc6-pci/arch/ppc/platforms/83xx/mpc834x_sys.c<BR>---
linux-2.6.13-rc6/arch/ppc/platforms/83xx/mpc834x_sys.c 2005-08-09
18:00:47.000000000 +0800<BR>+++
linux-2.6.13-rc6-pci/arch/ppc/platforms/83xx/mpc834x_sys.c 2005-08-30
16:38:52.000000000 +0800<BR>@@ -62,9 +62,28 @@<BR> unsigned char
__res[sizeof (bd_t)];<BR> <BR> #ifdef CONFIG_PCI<BR>-#error "PCI is
not supported"<BR>-/* NEED mpc83xx_map_irq &
mpc83xx_exclude_device<BR>- see platforms/85xx/mpc85xx_ads_common.c
*/<BR>+int<BR>+mpc83xx_ads_map_irq(struct pci_dev *dev,unsigned char
idsel,unsigned char pin)<BR>+{<BR>+ char
pci_irq_table[][4]=<BR>+ /*<BR>+ * PCI
IDSEL&INTPIN -> INTLINE<BR>+ *
INTA INTB INTC
INTD<BR>+ */<BR>+ {<BR>+ {PIRQA, PIRQB, PIRQC,
PIRQD}, /* idsel 0x11 */<BR>+ {PIRQC, PIRQD, PIRQA,
PIRQB}, /* idsel 0x12 */<BR>+ {PIRQD, PIRQA, PIRQB,
PIRQC} /* idsel 0x13 */<BR>+ };<BR>+ /* MPC8349 MDS board
specific */<BR>+ const long
min_idsel=0x11,max_idsel=0x13,irqs_per_slot=4;<BR>+ return
PCI_IRQ_TABLE_LOOKUP;<BR>+}<BR>+int<BR>+mpc83xx_ads_exclude_device(u_char bus,
u_char devfn)<BR>+{<BR>+ return PCIBIOS_SUCCESSFUL;<BR>+}<BR> #endif
/* CONFIG_PCI */<BR> <BR> /*
************************************************************************<BR>@@
-88,7 +107,7 @@<BR> <BR> #ifdef CONFIG_PCI<BR> /* setup PCI
host bridges
*/<BR>- mpc83xx_sys_setup_hose();<BR>+ mpc83xx_setup_hose();<BR> #endif<BR> mpc83xx_early_serial_map();<BR> <BR>@@
-175,10 +194,10 @@<BR> IRQ_SENSE_LEVEL, /* EXT 1
*/<BR> IRQ_SENSE_LEVEL, /* EXT 2
*/<BR> 0, /* EXT 3
*/<BR>- 0, /* EXT 4
*/<BR>- 0, /* EXT 5
*/<BR>- 0, /* EXT 6
*/<BR>- 0, /* EXT 7
*/<BR>+ IRQ_SENSE_LEVEL, /* EXT 4
*/<BR>+ IRQ_SENSE_LEVEL, /* EXT 5
*/<BR>+ IRQ_SENSE_LEVEL, /* EXT 6
*/<BR>+ IRQ_SENSE_LEVEL, /* EXT 7
*/<BR> };<BR> <BR> ipic_init(binfo->bi_immr_base +
0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);<BR>diff -urN -X dontdiff
linux-2.6.13-rc6/arch/ppc/platforms/83xx/mpc834x_sys.h
linux-2.6.13-rc6-pci/arch/ppc/platforms/83xx/mpc834x_sys.h<BR>---
linux-2.6.13-rc6/arch/ppc/platforms/83xx/mpc834x_sys.h 2005-06-18
03:48:29.000000000 +0800<BR>+++
linux-2.6.13-rc6-pci/arch/ppc/platforms/83xx/mpc834x_sys.h 2005-08-23
10:00:08.000000000 +0800<BR>@@ -26,7 +26,7 @@<BR> #define
VIRT_IMMRBAR ((uint)0xfe000000)<BR> <BR> #define
BCSR_PHYS_ADDR ((uint)0xf8000000)<BR>-#define
BCSR_SIZE ((uint)(32 * 1024))<BR>+#define
BCSR_SIZE
((uint)(128 * 1024))<BR> <BR> #define
BCSR_MISC_REG2_OFF 0x07<BR> #define
BCSR_MISC_REG2_PORESET 0x01<BR>@@ -35,22 +35,34 @@<BR> #define
BCSR_MISC_REG3_CNFLOCK 0x80<BR> <BR> #ifdef CONFIG_PCI<BR>-/* PCI
interrupt controller */<BR>-#define
PIRQA MPC83xx_IRQ_IRQ4<BR>-#define
PIRQB MPC83xx_IRQ_IRQ5<BR>-#define
PIRQC MPC83xx_IRQ_IRQ6<BR>-#define
PIRQD
MPC83xx_IRQ_IRQ7<BR>-<BR>-#define
MPC834x_SYS_PCI1_LOWER_IO
0x00000000<BR>-#define
MPC834x_SYS_PCI1_UPPER_IO
0x00ffffff<BR> <BR>-#define
MPC834x_SYS_PCI1_LOWER_MEM
0x80000000<BR>-#define
MPC834x_SYS_PCI1_UPPER_MEM
0x9fffffff<BR>+#define PCI1_CFG_ADDR_OFFSET (0x8300)<BR>+#define PCI1_CFG_DATA_OFFSET (0x8304)<BR> <BR>-#define
MPC834x_SYS_PCI1_IO_BASE
0xe2000000<BR>-#define MPC834x_SYS_PCI1_MEM_OFFSET
0x00000000<BR>+#define PCI2_CFG_ADDR_OFFSET (0x8380)<BR>+#define PCI2_CFG_DATA_OFFSET (0x8384)<BR>+<BR>+#define PIRQA MPC83xx_IRQ_EXT4<BR>+#define PIRQB MPC83xx_IRQ_EXT5<BR>+#define PIRQC MPC83xx_IRQ_EXT6<BR>+#define PIRQD MPC83xx_IRQ_EXT7<BR>+<BR>+#define MPC83xx_PCI1_LOWER_IO 0x00000000<BR>+#define MPC83xx_PCI1_UPPER_IO 0x00ffffff<BR>+#define MPC83xx_PCI1_LOWER_MEM 0x80000000<BR>+#define MPC83xx_PCI1_UPPER_MEM 0x9fffffff<BR>+#define MPC83xx_PCI1_IO_BASE 0xe2000000<BR>+#define MPC83xx_PCI1_MEM_OFFSET 0x00000000<BR>+#define MPC83xx_PCI1_IO_SIZE 0x01000000<BR>+<BR>+#define MPC83xx_PCI2_LOWER_IO 0x00000000<BR>+#define MPC83xx_PCI2_UPPER_IO 0x00ffffff<BR>+#define MPC83xx_PCI2_LOWER_MEM 0xa0000000<BR>+#define MPC83xx_PCI2_UPPER_MEM 0xbfffffff<BR>+#define MPC83xx_PCI2_IO_BASE 0xe3000000<BR>+#define MPC83xx_PCI2_MEM_OFFSET 0x00000000<BR>+#define MPC83xx_PCI2_IO_SIZE 0x01000000<BR> <BR>-#define
MPC834x_SYS_PCI1_IO_SIZE
0x01000000<BR> #endif /* CONFIG_PCI
*/<BR> <BR> #endif
/* __MACH_MPC83XX_SYS_H__ */<BR>diff -urN -X dontdiff
linux-2.6.13-rc6/arch/ppc/syslib/ppc834x_pci.h
linux-2.6.13-rc6-pci/arch/ppc/syslib/ppc834x_pci.h<BR>---
linux-2.6.13-rc6/arch/ppc/syslib/ppc834x_pci.h 1970-01-01
08:30:00.000000000 +0830<BR>+++
linux-2.6.13-rc6-pci/arch/ppc/syslib/ppc834x_pci.h 2005-08-19
18:30:11.000000000 +0800<BR>@@ -0,0 +1,161 @@<BR>+/* Created by Tony Li <<A
href="mailto:tony.li@freescale.com">tony.li@freescale.com</A>> 2005.6<BR>+ *
Copyright (c) 2005 freescale semiconductor<BR>+ *<BR>+ * This program is free
software; you can redistribute it and/or modify it<BR>+ * under the
terms of the GNU General Public License as published by the<BR>+ *
Free Software Foundation; either version 2 of the License, or (at
your<BR>+ * option) any later version.<BR>+ *<BR>+ * This program is distributed
in the hope that it will be useful, but<BR>+ * WITHOUT ANY WARRANTY; without
even the implied warranty of<BR>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU<BR>+ * General Public License for more details.<BR>+
*<BR>+ * You should have received a copy of the GNU General Public License
along<BR>+ * with this program; if not, write to the Free Software
Foundation, Inc.,<BR>+ * 675 Mass Ave, Cambridge, MA 02139, USA.<BR>+
*/<BR>+<BR>+#ifndef __MPC834X_PCI_H__<BR>+#define __MPC834X_PCI_H__<BR>+<BR>+typedef
struct immr_clk {<BR>+ u32 spmr; /* system PLL mode Register
*/<BR>+ u32 occr; /* output clock control Register
*/<BR>+ u32 sccr; /* system clock control Register
*/<BR>+ u8 res0[0xF4];<BR>+} immr_clk_t;<BR>+<BR>+/*<BR>+ * PCI Software
Configuration Registers<BR>+ */<BR>+typedef struct immr_pciconf {<BR>+ u32
config_address;<BR>+ u32 config_data;<BR>+ u32 int_ack;<BR>+ u8
res[116];<BR>+} immr_pciconf_t;<BR>+<BR>+/*<BR>+ * Sequencer<BR>+ */<BR>+typedef
struct immr_ios {<BR>+ u32 potar0;<BR>+ u8 res0[4];<BR>+ u32
pobar0;<BR>+ u8 res1[4];<BR>+ u32 pocmr0;<BR>+ u8
res2[4];<BR>+ u32
potar1;<BR>+ u8
res3[4];<BR>+ u32
pobar1;<BR>+ u8
res4[4];<BR>+ u32
pocmr1;<BR>+ u8
res5[4];<BR>+ u32
potar2;<BR>+ u8
res6[4];<BR>+ u32
pobar2;<BR>+ u8
res7[4];<BR>+ u32
pocmr2;<BR>+ u8
res8[4];<BR>+ u32
potar3;<BR>+ u8
res9[4];<BR>+ u32
pobar3;<BR>+ u8
res10[4];<BR>+ u32
pocmr3;<BR>+ u8
res11[4];<BR>+ u32
potar4;<BR>+ u8
res12[4];<BR>+ u32
pobar4;<BR>+ u8
res13[4];<BR>+ u32
pocmr4;<BR>+ u8
res14[4];<BR>+ u32
potar5;<BR>+ u8
res15[4];<BR>+ u32
pobar5;<BR>+ u8
res16[4];<BR>+ u32
pocmr5;<BR>+ u8 res17[4];<BR>+ u8
res18[0x60];<BR>+ u32 pmcr;<BR>+ u8 res19[4];<BR>+ u32
dtcr;<BR>+ u8 res20[4];<BR>+} immr_ios_t;<BR>+#define
POTAR_TA_MASK 0x000fffff<BR>+#define
POBAR_BA_MASK 0x000fffff<BR>+#define POCMR_EN 0x80000000<BR>+#define
POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */<BR>+#define
POCMR_SE 0x20000000 /* streaming enable */<BR>+#define
POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */<BR>+#define
POCMR_CM_MASK 0x000fffff<BR>+<BR>+/*<BR>+ * PCI Controller Control and
Status Registers<BR>+ */<BR>+typedef struct immr_pcictrl {<BR>+ u32
esr;<BR>+ u32 ecdr;<BR>+ u32 eer;<BR>+ u32 eatcr;<BR>+ u32
eacr;<BR>+ u32 eeacr;<BR>+ u32 edlcr;<BR>+ u32
edhcr;<BR>+ u32 gcr;<BR>+ u32 ecr;<BR>+ u32 gsr;<BR>+ u8
res0[12];<BR>+ u32 pitar2;<BR>+ u8 res1[4];<BR>+ u32
pibar2;<BR>+ u32 piebar2;<BR>+ u32 piwar2;<BR>+ u8
res2[4];<BR>+ u32 pitar1;<BR>+ u8 res3[4];<BR>+ u32
pibar1;<BR>+ u32 piebar1;<BR>+ u32 piwar1;<BR>+ u8
res4[4];<BR>+ u32 pitar0;<BR>+ u8 res5[4];<BR>+ u32
pibar0;<BR>+ u8 res6[4];<BR>+ u32 piwar0;<BR>+ u8
res7[132];<BR>+}
immr_pcictrl_t;<BR>+#define PITAR_TA_MASK 0x000fffff<BR>+#define PIBAR_MASK 0xffffffff<BR>+#define PIEBAR_EBA_MASK 0x000fffff<BR>+#define PIWAR_EN 0x80000000<BR>+#define PIWAR_PF 0x20000000<BR>+#define PIWAR_RTT_MASK 0x000f0000<BR>+#define PIWAR_RTT_NO_SNOOP 0x00040000<BR>+#define PIWAR_RTT_SNOOP 0x00050000<BR>+#define PIWAR_WTT_MASK 0x0000f000<BR>+#define PIWAR_WTT_NO_SNOOP 0x00004000<BR>+#define PIWAR_WTT_SNOOP 0x00005000<BR>+#define PIWAR_IWS_MASK 0x0000003F<BR>+#define PIWAR_IWS_4K 0x0000000B<BR>+#define PIWAR_IWS_8K 0x0000000C<BR>+#define PIWAR_IWS_16K 0x0000000D<BR>+#define PIWAR_IWS_32K 0x0000000E<BR>+#define PIWAR_IWS_64K 0x0000000F<BR>+#define PIWAR_IWS_128K 0x00000010<BR>+#define PIWAR_IWS_256K 0x00000011<BR>+#define PIWAR_IWS_512K 0x00000012<BR>+#define PIWAR_IWS_1M 0x00000013<BR>+#define PIWAR_IWS_2M 0x00000014<BR>+#define PIWAR_IWS_4M 0x00000015<BR>+#define PIWAR_IWS_8M 0x00000016<BR>+#define PIWAR_IWS_16M 0x00000017<BR>+#define PIWAR_IWS_32M 0x00000018<BR>+#define PIWAR_IWS_64M 0x00000019<BR>+#define PIWAR_IWS_128M 0x0000001A<BR>+#define PIWAR_IWS_256M 0x0000001B<BR>+#define PIWAR_IWS_512M 0x0000001C<BR>+#define PIWAR_IWS_1G 0x0000001D<BR>+#define PIWAR_IWS_2G 0x0000001E<BR>+<BR>+#endif
/*__MPC834X_PCI_H__*/<BR>diff -urN -X dontdiff
linux-2.6.13-rc6/arch/ppc/syslib/ppc83xx_setup.c
linux-2.6.13-rc6-pci/arch/ppc/syslib/ppc83xx_setup.c<BR>---
linux-2.6.13-rc6/arch/ppc/syslib/ppc83xx_setup.c 2005-08-09
18:00:47.000000000 +0800<BR>+++
linux-2.6.13-rc6-pci/arch/ppc/syslib/ppc83xx_setup.c 2005-08-23
10:18:04.000000000 +0800<BR>@@ -11,6 +11,20 @@<BR> * under the terms
of the GNU General Public License as published by the<BR> *
Free Software Foundation; either version 2 of the License, or (at
your<BR> * option) any later version.<BR>+ *<BR>+ * This program is
distributed in the hope that it will be useful, but<BR>+ * WITHOUT ANY WARRANTY;
without even the implied warranty of<BR>+ * MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU<BR>+ * General Public License for more
details.<BR>+ *<BR>+ * You should have received a copy of the GNU General
Public License along<BR>+ * with this program; if not, write to the Free
Software Foundation, Inc.,<BR>+ * 675 Mass Ave, Cambridge, MA 02139, USA.<BR>+
*<BR>+ * July 2005, Tony Li<<A
href="mailto:tony.li@freescale.com">tony.li@freescale.com</A>><BR>+
* Added PCI support<BR>+ * PCI can be enabled only
if MPC834x SYS board combined with PIB(Platform<BR>+ * IO Board) board in which
three physical PCI slots locate.<BR> */<BR> <BR> #include
<linux/config.h><BR>@@ -19,7 +33,7 @@<BR> #include
<linux/init.h><BR> #include <linux/pci.h><BR> #include
<linux/serial.h><BR>-#include <linux/tty.h> /* for
linux/serial_core.h */<BR>+#include <linux/tty.h> /* for
linux/serial_core.h */<BR> #include
<linux/serial_core.h><BR> #include
<linux/serial_8250.h><BR> <BR>@@ -31,27 +45,29 @@<BR> #include
<asm/delay.h><BR> <BR> #include
<syslib/ppc83xx_setup.h><BR>+#if defined(CONFIG_PCI)<BR>+#include
<asm/delay.h><BR>+#include
<syslib/ppc834x_pci.h><BR>+#endif<BR> <BR> phys_addr_t
immrbar;<BR> <BR> /* Return the amount of memory */<BR>-unsigned long
__init<BR>-mpc83xx_find_end_of_memory(void)<BR>+unsigned long __init
mpc83xx_find_end_of_memory(void)<BR> {<BR>-
bd_t *binfo;<BR>+ bd_t
*binfo;<BR> <BR>- binfo = (bd_t
*) __res;<BR>+ binfo = (bd_t *)
__res;<BR> <BR>- return
binfo->bi_memsize;<BR>+ return
binfo->bi_memsize;<BR> }<BR> <BR>-long
__init<BR>-mpc83xx_time_init(void)<BR>+long __init
mpc83xx_time_init(void)<BR> {<BR> #define SPCR_OFFS
0x00000110<BR> #define SPCR_TBEN
0x00400000<BR> <BR>- bd_t *binfo = (bd_t *)__res;<BR>+ bd_t
*binfo = (bd_t *) __res;<BR> u32 *spcr =
ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);<BR> <BR> *spcr
|= SPCR_TBEN;<BR>@@ -62,11 +78,10 @@<BR> }<BR> <BR> /* The
decrementer counts at the system (internal) clock freq divided by 4 */<BR>-void
__init<BR>-mpc83xx_calibrate_decr(void)<BR>+void __init
mpc83xx_calibrate_decr(void)<BR> {<BR>-
bd_t *binfo = (bd_t *) __res;<BR>-
unsigned int freq, divisor;<BR>+ bd_t *binfo = (bd_t *)
__res;<BR>+ unsigned int freq, divisor;<BR> <BR> freq =
binfo->bi_busfreq;<BR> divisor = 4;<BR>@@ -75,15 +90,14
@@<BR> }<BR> <BR> #ifdef CONFIG_SERIAL_8250<BR>-void
__init<BR>-mpc83xx_early_serial_map(void)<BR>+void __init
mpc83xx_early_serial_map(void)<BR> {<BR> #if
defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)<BR> struct
uart_port serial_req;<BR> #endif<BR> struct plat_serial8250_port
*pdata;<BR> bd_t *binfo = (bd_t *) __res;<BR>- pdata = (struct
plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);<BR>+ pdata =
(struct plat_serial8250_port
*)ppc_sys_get_pdata(MPC83xx_DUART);<BR> <BR> /* Setup serial
port access */<BR> pdata[0].uartclk = binfo->bi_busfreq;<BR>@@
-91,7 +105,7 @@<BR> pdata[0].membase = ioremap(pdata[0].mapbase,
0x100);<BR> <BR> #if defined(CONFIG_SERIAL_TEXT_DEBUG) ||
defined(CONFIG_KGDB)<BR>- memset(&serial_req, 0, sizeof
(serial_req));<BR>+ memset(&serial_req, 0,
sizeof(serial_req));<BR> serial_req.iotype =
SERIAL_IO_MEM;<BR> serial_req.mapbase =
pdata[0].mapbase;<BR> serial_req.membase = pdata[0].membase;<BR>@@
-114,8 +128,7
@@<BR> }<BR> #endif<BR> <BR>-void<BR>-mpc83xx_restart(char
*cmd)<BR>+void mpc83xx_restart(char *cmd)<BR> {<BR> volatile
unsigned char __iomem *reg;<BR> unsigned char tmp;<BR>@@ -129,7
+142,7 @@<BR> * Otherwise the reset asserts but doesn't
clear.<BR> */<BR> tmp = in_8(reg +
BCSR_MISC_REG3_OFF);<BR>- tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high
false */<BR>+ tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false
*/<BR> out_8(reg + BCSR_MISC_REG3_OFF,
tmp);<BR> <BR> /*<BR>@@ -145,21 +158,252 @@<BR> tmp
|= BCSR_MISC_REG2_PORESET;<BR> out_8(reg + BCSR_MISC_REG2_OFF,
tmp);<BR> <BR>- for(;;);<BR>+ for (;;)
;<BR> }<BR> <BR>-void<BR>-mpc83xx_power_off(void)<BR>+void
mpc83xx_power_off(void)<BR> {<BR> local_irq_disable();<BR>- for(;;);<BR>+ for
(;;) ;<BR> }<BR> <BR>-void<BR>-mpc83xx_halt(void)<BR>+void
mpc83xx_halt(void)<BR> {<BR> local_irq_disable();<BR>- for(;;);<BR>+ for
(;;) ;<BR>+}<BR>+<BR>+#if defined(CONFIG_PCI)<BR>+void __init
mpc83xx_setup_pci1(struct pci_controller *hose)<BR>+{<BR>+ unsigned short
reg16;<BR>+ volatile immr_pcictrl_t *pci_ctrl;<BR>+ volatile
immr_ios_t *ios;<BR>+ bd_t *binfo = (bd_t *) __res;<BR>+<BR>+ pci_ctrl
= ioremap(binfo->bi_immr_base + 0x8500,<BR>+
sizeof(immr_pcictrl_t));<BR>+ ios = ioremap(binfo->bi_immr_base +
0x8400, sizeof(immr_ios_t));<BR>+<BR>+ /*<BR>+ * Configure PCI
Outbound Translation Windows<BR>+ */<BR>+ ios->potar0 =
(MPC83xx_PCI1_LOWER_MEM >> 12) &
POTAR_TA_MASK;<BR>+ ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12)
& POBAR_BA_MASK;<BR>+ ios->pocmr0 = POCMR_EN
|<BR>+ (((~0UL
-<BR>+ (MPC83xx_PCI1_UPPER_MEM
-<BR>+ MPC83xx_PCI1_LOWER_MEM)) >> 12) &
POCMR_CM_MASK);<BR>+<BR>+ /* mapped to PCI1 IO space 0x0 to local
0xe2000000 */<BR>+ ios->potar1 = (MPC83xx_PCI1_LOWER_IO >>
12) & POTAR_TA_MASK;<BR>+ ios->pobar1 = (MPC83xx_PCI1_IO_BASE
>> 12) & POBAR_BA_MASK;<BR>+ ios->pocmr1 = POCMR_EN | POCMR_IO
|<BR>+ (((~0UL
-<BR>+ (MPC83xx_PCI1_UPPER_IO
-<BR>+ MPC83xx_PCI1_LOWER_IO)) >> 12) &
POCMR_CM_MASK);<BR>+<BR>+ /*<BR>+ * Configure PCI Inbound Translation
Windows<BR>+ */<BR>+ pci_ctrl->pitar1 =
0x0;<BR>+ pci_ctrl->pibar1 = 0x0;<BR>+ pci_ctrl->piebar1 =
0x0;<BR>+ pci_ctrl->piwar1 =<BR>+ PIWAR_EN |
PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |<BR>+
PIWAR_IWS_2G;<BR>+<BR>+ /*<BR>+ * Release PCI RST signal<BR>+
*/<BR>+ pci_ctrl->gcr =
0;<BR>+ udelay(2000);<BR>+ pci_ctrl->gcr =
1;<BR>+ udelay(2000);<BR>+<BR>+ reg16 =
0xff;<BR>+ early_read_config_word(hose, hose->first_busno, 0,
PCI_COMMAND, &reg16);<BR>+ reg16 |= PCI_COMMAND_SERR |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;<BR>+ early_write_config_word(hose,
hose->first_busno, 0, PCI_COMMAND, reg16);<BR>+<BR>+ /*<BR>+ *
Clear non-reserved bits in status register.<BR>+
*/<BR>+ early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS,
0xffff);<BR>+ early_write_config_byte(hose, hose->first_busno, 0,
PCI_LATENCY_TIMER,<BR>+ 0x80);<BR> }<BR> <BR>-/*
PCI SUPPORT DOES NOT EXIT, MODEL after ppc85xx_setup.c */<BR>+void __init
mpc834x_ads_setup_pci2(struct pci_controller *hose)<BR>+{<BR>+ unsigned
short reg16;<BR>+ volatile immr_pcictrl_t *pci_ctrl;<BR>+ volatile
immr_ios_t *ios;<BR>+ bd_t *binfo = (bd_t *) __res;<BR>+<BR>+ pci_ctrl
= ioremap(binfo->bi_immr_base + 0x8600,<BR>+
sizeof(immr_pcictrl_t));<BR>+ ios = ioremap(binfo->bi_immr_base +
0x8400, sizeof(immr_ios_t));<BR>+<BR>+ /*<BR>+ * Configure PCI
Outbound Translation Windows<BR>+ */<BR>+ ios->potar3 =
(MPC83xx_PCI2_LOWER_MEM >> 12) &
POTAR_TA_MASK;<BR>+ ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12)
& POBAR_BA_MASK;<BR>+ ios->pocmr3 = POCMR_EN | POCMR_DST
|<BR>+ (((~0UL
-<BR>+ (MPC83xx_PCI2_UPPER_MEM
-<BR>+ MPC83xx_PCI2_LOWER_MEM)) >> 12) &
POCMR_CM_MASK);<BR>+<BR>+ /* mapped to PCI2 IO space 0x0 to local
0xe3000000 */<BR>+ ios->potar4 = (MPC83xx_PCI2_LOWER_IO >>
12) & POTAR_TA_MASK;<BR>+ ios->pobar4 = (MPC83xx_PCI2_IO_BASE
>> 12) & POBAR_BA_MASK;<BR>+ ios->pocmr4 = POCMR_EN |
POCMR_DST | POCMR_IO |<BR>+ (((~0UL
-<BR>+ (MPC83xx_PCI2_UPPER_IO
-<BR>+ MPC83xx_PCI2_LOWER_IO)) >> 12) &
POCMR_CM_MASK);<BR>+<BR>+ /*<BR>+ * Configure PCI Inbound Translation
Windows<BR>+ */<BR>+ pci_ctrl->pitar1 =
0x0;<BR>+ pci_ctrl->pibar1 = 0x0;<BR>+ pci_ctrl->piebar1 =
0x0;<BR>+ pci_ctrl->piwar1 =<BR>+ PIWAR_EN |
PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |<BR>+
PIWAR_IWS_2G;<BR>+<BR>+ /*<BR>+ * Release PCI RST signal<BR>+
*/<BR>+ pci_ctrl->gcr =
0;<BR>+ udelay(2000);<BR>+ pci_ctrl->gcr =
1;<BR>+ udelay(2000);<BR>+<BR>+ reg16 =
0xff;<BR>+ early_read_config_word(hose, hose->first_busno, 0,
PCI_COMMAND, &reg16);<BR>+ reg16 |= PCI_COMMAND_SERR |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;<BR>+ early_write_config_word(hose,
hose->first_busno, 0, PCI_COMMAND, reg16);<BR>+<BR>+ /*<BR>+ *
Clear non-reserved bits in status register.<BR>+
*/<BR>+ early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS,
0xffff);<BR>+ early_write_config_byte(hose, hose->first_busno, 0,
PCI_LATENCY_TIMER,<BR>+ 0x80);<BR>+}<BR>+<BR>+extern int
mpc83xx_ads_map_irq(struct pci_dev *dev, unsigned char
idsel,<BR>+ unsigned char
pin);<BR>+extern int mpc83xx_ads_exclude_device(u_char bus, u_char
devfn);<BR>+<BR>+/*<BR>+ * PCI buses can be enabled only if SYS board combinates
with PIB(Platform IO Board) board<BR>+ * which provide 3 PCI slots. There is 2
PCI buses and 3 PCI slots,so people must configure<BR>+ * the routes between
them before enable PCI bus. This routes are under the control of PCA9555PW <BR>+
* device which can be accessed via I2C bus 2 and are configured by firmware.
Refer to Freescale to<BR>+ * get more information about firmware
configuration.<BR>+ */<BR>+void __init
mpc83xx_setup_hose(void)<BR>+{<BR>+ unsigned long val32;<BR>+ volatile
immr_clk_t *clk;<BR>+ volatile struct pci_controller *hose1;<BR>+#ifdef
CONFIG_MPC834x_PCI2<BR>+ volatile struct pci_controller
*hose2;<BR>+#endif<BR>+ volatile bd_t *binfo = (bd_t *)
__res;<BR>+<BR>+ clk = ioremap(binfo->bi_immr_base + 0xA00,
sizeof(immr_clk_t));<BR>+<BR>+ /*<BR>+ * Configure PCI controller and
PCI_CLK_OUTPUT both in 66M mode<BR>+ */<BR>+ val32 =
clk->occr;<BR>+ udelay(2000);<BR>+ clk->occr =
0xff000000;<BR>+ udelay(2000);<BR>+<BR>+ hose1 =
pcibios_alloc_controller();<BR>+ if
(!hose1)<BR>+ return;<BR>+<BR>+ ppc_md.pci_swizzle =
common_swizzle;<BR>+ ppc_md.pci_map_irq =
mpc83xx_ads_map_irq;<BR>+<BR>+ hose1->bus_offset =
0;<BR>+ hose1->first_busno = 0;<BR>+ hose1->last_busno =
0xff;<BR>+<BR>+ setup_indirect_pci(hose1, binfo->bi_immr_base +
PCI1_CFG_ADDR_OFFSET,<BR>+ binfo->bi_immr_base
+ PCI1_CFG_DATA_OFFSET);<BR>+ hose1->set_cfg_type =
1;<BR>+<BR>+ mpc83xx_setup_pci1(hose1);<BR>+<BR>+ hose1->pci_mem_offset
= MPC83xx_PCI1_MEM_OFFSET;<BR>+ hose1->mem_space.start =
MPC83xx_PCI1_LOWER_MEM;<BR>+ hose1->mem_space.end =
MPC83xx_PCI1_UPPER_MEM;<BR>+<BR>+ hose1->io_base_phys =
MPC83xx_PCI1_IO_BASE;<BR>+ hose1->io_space.start =
MPC83xx_PCI1_LOWER_IO;<BR>+ hose1->io_space.end =
MPC83xx_PCI1_UPPER_IO;<BR>+#ifdef CONFIG_MPC834x_PCI2<BR>+ isa_io_base =
(unsigned
long)ioremap(MPC83xx_PCI1_IO_BASE,<BR>+
MPC83xx_PCI1_IO_SIZE
+<BR>+
MPC83xx_PCI2_IO_SIZE);<BR>+#else<BR>+ isa_io_base = (unsigned
long)ioremap(MPC83xx_PCI1_IO_BASE,<BR>+
MPC83xx_PCI1_IO_SIZE);<BR>+#endif /* CONFIG_MPC834x_PCI2
*/<BR>+ hose1->io_base_virt = (void *)isa_io_base;<BR>+ /* setup
resources
*/<BR>+ pci_init_resource(&hose1->io_resource,<BR>+
MPC83xx_PCI1_LOWER_IO,<BR>+
MPC83xx_PCI1_UPPER_IO,<BR>+ IORESOURCE_IO, "PCI host
bridge
1");<BR>+ pci_init_resource(&hose1->mem_resources[0],<BR>+
MPC83xx_PCI1_LOWER_MEM,<BR>+
MPC83xx_PCI1_UPPER_MEM,<BR>+ IORESOURCE_MEM, "PCI host
bridge 1");<BR>+<BR>+ ppc_md.pci_exclude_device =
mpc83xx_ads_exclude_device;<BR>+ hose1->last_busno =
pciauto_bus_scan(hose1, hose1->first_busno);<BR>+<BR>+#ifdef
CONFIG_MPC834x_PCI2<BR>+ hose2 = pcibios_alloc_controller();<BR>+ if
(!hose2)<BR>+ return;<BR>+<BR>+ hose2->bus_offset =
hose1->last_busno + 1;<BR>+ hose2->first_busno = hose1->last_busno
+ 1;<BR>+ hose2->last_busno = 0xff;<BR>+ setup_indirect_pci(hose2,
binfo->bi_immr_base +
PCI2_CFG_ADDR_OFFSET,<BR>+ binfo->bi_immr_base
+ PCI2_CFG_DATA_OFFSET);<BR>+ hose2->set_cfg_type =
1;<BR>+<BR>+ mpc834x_ads_setup_pci2(hose2);<BR>+<BR>+ hose2->pci_mem_offset
= MPC83xx_PCI2_MEM_OFFSET;<BR>+ hose2->mem_space.start =
MPC83xx_PCI2_LOWER_MEM;<BR>+ hose2->mem_space.end =
MPC83xx_PCI2_UPPER_MEM;<BR>+<BR>+ hose2->io_base_phys =
MPC83xx_PCI2_IO_BASE;<BR>+ hose2->io_space.start =
MPC83xx_PCI2_LOWER_IO;<BR>+ hose2->io_space.end =
MPC83xx_PCI2_UPPER_IO;<BR>+ hose2->io_base_virt = (void *)(isa_io_base +
MPC83xx_PCI1_IO_SIZE);<BR>+ /* setup resources
*/<BR>+ pci_init_resource(&hose2->io_resource,<BR>+
MPC83xx_PCI2_LOWER_IO,<BR>+
MPC83xx_PCI2_UPPER_IO,<BR>+ IORESOURCE_IO, "PCI host
bridge
2");<BR>+ pci_init_resource(&hose2->mem_resources[0],<BR>+
MPC83xx_PCI2_LOWER_MEM,<BR>+
MPC83xx_PCI2_UPPER_MEM,<BR>+ IORESOURCE_MEM, "PCI host
bridge 2");<BR>+<BR>+ hose2->last_busno = pciauto_bus_scan(hose2,
hose2->first_busno);<BR>+#endif /* CONFIG_MPC834x_PCI2
*/<BR>+}<BR>+#endif /*CONFIG_PCI */<BR>diff -urN -X
dontdiff linux-2.6.13-rc6/arch/ppc/syslib/ppc83xx_setup.h
linux-2.6.13-rc6-pci/arch/ppc/syslib/ppc83xx_setup.h<BR>---
linux-2.6.13-rc6/arch/ppc/syslib/ppc83xx_setup.h 2005-06-18
03:48:29.000000000 +0800<BR>+++
linux-2.6.13-rc6-pci/arch/ppc/syslib/ppc83xx_setup.h 2005-08-23
10:25:43.000000000 +0800<BR>@@ -12,6 +12,14 @@<BR> * Free Software
Foundation; either version 2 of the License, or (at your<BR> *
option) any later version.<BR> *<BR>+ * This program is distributed in the
hope that it will be useful, but<BR>+ * WITHOUT ANY WARRANTY; without even the
implied warranty of<BR>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU<BR>+ * General Public License for more details.<BR>+
*<BR>+ * You should have received a copy of the GNU General Public License
along<BR>+ * with this program; if not, write to the Free Software
Foundation, Inc.,<BR>+ * 675 Mass Ave, Cambridge, MA 02139, USA.<BR>
*/<BR> <BR> #ifndef __PPC_SYSLIB_PPC83XX_SETUP_H<BR>@@ -20,6 +28,7
@@<BR> #include <linux/config.h><BR> #include
<linux/init.h><BR> #include <asm/ppcboot.h><BR>+#include
<asm/mpc83xx.h><BR> <BR> extern unsigned long
mpc83xx_find_end_of_memory(void) __init;<BR> extern long
mpc83xx_time_init(void) __init;<BR>@@ -30,15 +39,6 @@<BR> extern void
mpc83xx_halt(void);<BR> extern void mpc83xx_setup_hose(void)
__init;<BR> <BR>-/* PCI config */<BR>-#if 0<BR>-#define
PCI1_CFG_ADDR_OFFSET (FIXME)<BR>-#define
PCI1_CFG_DATA_OFFSET (FIXME)<BR>-<BR>-#define
PCI2_CFG_ADDR_OFFSET (FIXME)<BR>-#define
PCI2_CFG_DATA_OFFSET (FIXME)<BR>-#endif<BR>-<BR> /* Serial Config
*/<BR> #ifdef CONFIG_SERIAL_MANY_PORTS<BR> #define RS_TABLE_SIZE
64<BR>@@ -50,4 +50,4 @@<BR> #define BASE_BAUD
115200<BR> #endif<BR> <BR>-#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H
*/<BR>+#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H
*/<BR></FONT></DIV></BODY></HTML>