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Schaefer-Hutter, Peter wrote:
<blockquote
cite="mid8E342283C2100540AAC5D103097054776F8533@rcexc.racoms.loc"
type="cite">
<pre wrap="">Hello,
</pre>
<blockquote type="cite">
<pre wrap="">From: Vitaly Bordug [<a class="moz-txt-link-freetext" href="mailto:vbordug@ru.mvista.com">mailto:vbordug@ru.mvista.com</a>]
</pre>
</blockquote>
<pre wrap=""><!---->
</pre>
<blockquote type="cite">
<pre wrap="">The board does not hang - there's somithing with
console since you don't see anything. Try to change
BCSR_ADDR from 0xf4500000 to 0xf80...0 - the newer
version of the boards may have this changed.
</pre>
</blockquote>
<pre wrap=""><!---->
Hrm... arc/ppc/mpc885ads.h already reads
/* U-Boot maps BCSR to 0xff080000 */
#define BCSR_ADDR ((uint)0xff080000)
And that's the same setting that my 2.4-Kernel
uses, so it should work with 0xff080000.
However, BCSR_SIZE looks suspicious in this header:
#define BCSR_SIZE ((uint)32)
Shouldn't that read:
#define BCSR_SIZE ((uint)32 * 1024)
??!?
Regards,
Peter
</pre>
</blockquote>
<quotation> (This is from 8272 User Guide, but 885 I guess is the
same in this part)<br>
<blockquote
cite="mid8E342283C2100540AAC5D103097054776F8533@rcexc.racoms.loc"
type="cite">Most of the hardware options on the MPC8272ADS are
controlled or monitored by the<br>
BCSR, which is a 32 bit wide read / write register file. The BCSR is
accessed via the<br>
MPC8272s’ memory controller (see Table 5-5) and in fact includes 8
registers: BCSR0 to<br>
BCSR7. Since the minimum block size for a CS region is 32KBytes and
only A(27:29)<br>
lines are decoded by the BCSR for register selection, BCSR0 - BCSR7 are
duplicated inside<br>
that region.</blockquote>
<quotation\><br>
<br>
<pre class="moz-signature" cols="72">--
Sincerely,
Vitaly
</pre>
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