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<DIV align=left><FONT face='Arial' color=#000000 size=2>Subject: PPC8272 - FCC2 transmitter
underrun<BR><BR>Description: On a board with PPC8272 we get "transmitter
underrun" interrupt from the FCC2.<BR><BR>The BD and Buffers are on an external
RAM on the 60x.<BR><BR>It looks like getting the READY bit in the current BD
with a perfectly good Buffer immidiatly brings up the
interrupt.<BR></FONT></DIV>
<DIV align=left><FONT face=Arial color=#000000 size=2></FONT> </DIV>
<DIV align=left><FONT face=Arial color=#000000 size=2></FONT> </DIV>
<DIV align=left><FONT face=Arial color=#000000 size=2>there are two underrun
reasons :<BR><BR>1.<BR>If TxBD[L] (last buffer in the frame) is cleared when the
end of the BD is reached and the<BR>transmitter moves immediately to the next
buffer to begin transmission. Failure to provide the<BR>next buffer in time
causes a transmit underrun.<BR><BR><BR>2.<BR>If the CPM is heavy loaded and
(because of bus latency) the SDMA cannot fill the FIFO<BR>from external memory,
a transmit underrun occurs. </FONT></DIV>
<DIV align=left><FONT face=Arial color=#000000 size=2></FONT> </DIV>
<DIV align=left><FONT face=Arial color=#000000 size=2>But i've stepped with an
ice and checked both -looked at the L bit and halted the cpu right after the
setting of the Ready bit.</DIV></FONT></BODY></HTML>