<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii">
<TITLE>Message</TITLE>
<META content="MSHTML 6.00.2800.1400" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=754450621-25042005><FONT face=Arial
size=2>Hi.</FONT></SPAN></DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial size=2>I am trying to
figure out where in the PowerPC kernel the HID1 register is updated to enable
bits dealing with cache coherency in an SMP system. Grepping through
the arch/ppc source does not reveal much.</FONT></SPAN></DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial size=2>I have two
7447A processors and somewhere the ABE and SYNCBE bits in HID1 need to be
turned on to enable cache coherency. Is supposed to happen in the
bootloader prior to the kernel running??</FONT></SPAN></DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial
size=2>Thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=754450621-25042005><FONT face=Arial size=2>Stuart
Yoder</FONT></SPAN></DIV></BODY></HTML>