405 MII-PHY communication problem (was: Re: PPC405gp enet Soft Reset)

[Stefan Roese]

David,

just to let you know:

We have PPC405GP Rev D & Rev E running @ 198 MHz with Intel LXT971LE @
address 0, and seem to have none of your described problem:

=> mii info
PHY 0x00: OUI = 0x04DE, Model = 0x0E, Rev = 0x01, 100baseT, FDX
read err 3
a2: read: EMAC_STACR=0xffffc023, i=3
read err 3
a2: read: EMAC_STACR=0xffffc043, i=3
read err 3

etc...

Stefan Roese


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